riscv/rocket-chip
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final Reg changes

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This commit is contained in:
Henry Cook
2013-08-15 15:28:15 -07:00
parent b570435847
commit 3a266cbbfa
16 changed files with 117 additions and 117 deletions
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2
rocket/src/main/scala/dpath.scala
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@ -50,7 +50,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
val wb_reg_inst = Reg(Bits())
val wb_reg_waddr = Reg(UInt())
val wb_reg_wdata = Reg(Bits())
val wb_reg_ll_wb = RegReset(Bool(false))
val wb_reg_ll_wb = Reg(init=Bool(false))
val wb_wdata = Bits()
val wb_reg_store_data = Reg(Bits())
val wb_reg_rs1 = Reg(Bits())