riscv/rocket-chip
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final Reg changes

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This commit is contained in:
Henry Cook
2013-08-15 15:28:15 -07:00
parent b570435847
commit 3a266cbbfa
16 changed files with 117 additions and 117 deletions
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98
rocket/src/main/scala/ctrl.scala
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@ -355,59 +355,59 @@ class Control(implicit conf: RocketConfiguration) extends Module
val id_waddr = Mux(id_sel_wa === WA_RA, RA, io.dpath.inst(31,27));
val id_load_use = Bool();
val ex_reg_xcpt_interrupt = RegReset(Bool(false))
val ex_reg_valid = RegReset(Bool(false))
val ex_reg_eret = RegReset(Bool(false))
val ex_reg_wen = RegReset(Bool(false))
val ex_reg_fp_wen = RegReset(Bool(false))
val ex_reg_flush_inst = RegReset(Bool(false))
val ex_reg_jalr = RegReset(Bool(false))
val ex_reg_btb_hit = RegReset(Bool(false))
val ex_reg_div_mul_val = RegReset(Bool(false))
val ex_reg_mem_val = RegReset(Bool(false))
val ex_reg_xcpt = RegReset(Bool(false))
val ex_reg_fp_val = RegReset(Bool(false))
val ex_reg_vec_val = RegReset(Bool(false))
val ex_reg_replay_next = RegReset(Bool(false))
val ex_reg_load_use = RegReset(Bool(false))
val ex_reg_pcr = RegReset(PCR.N)
val ex_reg_br_type = RegReset(BR_N)
val ex_reg_xcpt_interrupt = Reg(init=Bool(false))
val ex_reg_valid = Reg(init=Bool(false))
val ex_reg_eret = Reg(init=Bool(false))
val ex_reg_wen = Reg(init=Bool(false))
val ex_reg_fp_wen = Reg(init=Bool(false))
val ex_reg_flush_inst = Reg(init=Bool(false))
val ex_reg_jalr = Reg(init=Bool(false))
val ex_reg_btb_hit = Reg(init=Bool(false))
val ex_reg_div_mul_val = Reg(init=Bool(false))
val ex_reg_mem_val = Reg(init=Bool(false))
val ex_reg_xcpt = Reg(init=Bool(false))
val ex_reg_fp_val = Reg(init=Bool(false))
val ex_reg_vec_val = Reg(init=Bool(false))
val ex_reg_replay_next = Reg(init=Bool(false))
val ex_reg_load_use = Reg(init=Bool(false))
val ex_reg_pcr = Reg(init=PCR.N)
val ex_reg_br_type = Reg(init=BR_N)
val ex_reg_mem_cmd = Reg(Bits())
val ex_reg_mem_type = Reg(Bits())
val ex_reg_cause = Reg(UInt())
val mem_reg_xcpt_interrupt = RegReset(Bool(false))
val mem_reg_valid = RegReset(Bool(false))
val mem_reg_eret = RegReset(Bool(false))
val mem_reg_wen = RegReset(Bool(false))
val mem_reg_fp_wen = RegReset(Bool(false))
val mem_reg_flush_inst = RegReset(Bool(false))
val mem_reg_div_mul_val = RegReset(Bool(false))
val mem_reg_mem_val = RegReset(Bool(false))
val mem_reg_xcpt = RegReset(Bool(false))
val mem_reg_fp_val = RegReset(Bool(false))
val mem_reg_vec_val = RegReset(Bool(false))
val mem_reg_replay = RegReset(Bool(false))
val mem_reg_replay_next = RegReset(Bool(false))
val mem_reg_pcr = RegReset(PCR.N)
val mem_reg_xcpt_interrupt = Reg(init=Bool(false))
val mem_reg_valid = Reg(init=Bool(false))
val mem_reg_eret = Reg(init=Bool(false))
val mem_reg_wen = Reg(init=Bool(false))
val mem_reg_fp_wen = Reg(init=Bool(false))
val mem_reg_flush_inst = Reg(init=Bool(false))
val mem_reg_div_mul_val = Reg(init=Bool(false))
val mem_reg_mem_val = Reg(init=Bool(false))
val mem_reg_xcpt = Reg(init=Bool(false))
val mem_reg_fp_val = Reg(init=Bool(false))
val mem_reg_vec_val = Reg(init=Bool(false))
val mem_reg_replay = Reg(init=Bool(false))
val mem_reg_replay_next = Reg(init=Bool(false))
val mem_reg_pcr = Reg(init=PCR.N)
val mem_reg_cause = Reg(UInt())
val mem_reg_slow_bypass = Reg(Bool())
val wb_reg_valid = RegReset(Bool(false))
val wb_reg_pcr = RegReset(PCR.N)
val wb_reg_wen = RegReset(Bool(false))
val wb_reg_fp_wen = RegReset(Bool(false))
val wb_reg_flush_inst = RegReset(Bool(false))
val wb_reg_mem_val = RegReset(Bool(false))
val wb_reg_eret = RegReset(Bool(false))
val wb_reg_xcpt = RegReset(Bool(false))
val wb_reg_replay = RegReset(Bool(false))
val wb_reg_valid = Reg(init=Bool(false))
val wb_reg_pcr = Reg(init=PCR.N)
val wb_reg_wen = Reg(init=Bool(false))
val wb_reg_fp_wen = Reg(init=Bool(false))
val wb_reg_flush_inst = Reg(init=Bool(false))
val wb_reg_mem_val = Reg(init=Bool(false))
val wb_reg_eret = Reg(init=Bool(false))
val wb_reg_xcpt = Reg(init=Bool(false))
val wb_reg_replay = Reg(init=Bool(false))
val wb_reg_cause = Reg(UInt())
val wb_reg_fp_val = RegReset(Bool(false))
val wb_reg_div_mul_val = RegReset(Bool(false))
val wb_reg_fp_val = Reg(init=Bool(false))
val wb_reg_div_mul_val = Reg(init=Bool(false))
val take_pc = Bool()
val pc_taken = RegUpdate(take_pc, Bool(false))
val pc_taken = Reg(next=take_pc, init=Bool(false))
val take_pc_wb = Bool()
val ctrl_killd = Bool()
val ctrl_killx = Bool()
@ -611,17 +611,17 @@ class Control(implicit conf: RocketConfiguration) extends Module
class Scoreboard(n: Int)
{
val r = RegReset(Bits(0, n))
var next = r
val r = Reg(init=Bits(0, n))
var _next = r
var ens = Bool(false)
def apply(addr: UInt) = r(addr)
def set(en: Bool, addr: UInt): Unit = update(en, next | mask(en, addr))
def clear(en: Bool, addr: UInt): Unit = update(en, next & ~mask(en, addr))
def set(en: Bool, addr: UInt): Unit = update(en, _next | mask(en, addr))
def clear(en: Bool, addr: UInt): Unit = update(en, _next & ~mask(en, addr))
private def mask(en: Bool, addr: UInt) = Mux(en, UInt(1) << addr, UInt(0))
private def update(en: Bool, update: UInt) = {
next = update
_next = update
ens = ens || en
when (ens) { r := next }
when (ens) { r := _next }
}
}