final Reg changes

2013-08-15 15:28:15 -07:00
parent b570435847
commit 3a266cbbfa
16 changed files with 117 additions and 117 deletions
--- a/rocket/src/main/scala/core.scala
+++ b/rocket/src/main/scala/core.scala
@ -42,7 +42,7 @@ class Core(implicit conf: RocketConfiguration) extends Module
  } else null

  if (conf.vec) {
-    val vu = Module(new vu(RegUpdate(reset)))
+    val vu = Module(new vu(Reg(next=reset)))

    val vdtlb = Module(new TLB(8))
    ptw += vdtlb.io.ptw