riscv/rocket-chip
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Use Chisel 3 to build verilog on Travis

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Chisel 3 can't build the C++ emulator, so we currently can't have direct
support for testing RocketChip.  We can at least test to see if the
Verilog builds when run through Chisel 3, which this patch does.
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Palmer Dabbelt authored and Palmer Dabbelt committed 2016-03-24 12:00:13 -07:00
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commit 39cf945efb
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.travis.yml
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@@ -63,7 +63,7 @@ before_install:
- export CXX=g++-4.8 CC=gcc-4.8
script:
- make vsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
- make vsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default CHISEL_VERSION=3
- make fsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
- make emulator-ndebug -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
- make emulator-asm-tests -C regression CONFIG=$CONFIG TORTURE_CONFIG=default