strip DMA and RoCC CSRs out of rocket and uncore (#201)
This commit is contained in:
Howard Mao
committed by
Andrew Waterman
Andrew Waterman
parent
47a0c880a4
commit
38e0967816
@ -1,535 +0,0 @@
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package uncore.devices
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import Chisel._
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import cde.{Parameters, Field}
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import junctions._
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import junctions.NastiConstants._
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import uncore.tilelink._
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import uncore.Util._
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case object NDmaTransactors extends Field[Int]
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case object NDmaXacts extends Field[Int]
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case object NDmaClients extends Field[Int]
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trait HasDmaParameters {
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implicit val p: Parameters
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val nDmaTransactors = p(NDmaTransactors)
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val nDmaXacts = p(NDmaXacts)
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val nDmaClients = p(NDmaClients)
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val dmaXactIdBits = log2Up(nDmaXacts)
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val dmaClientIdBits = log2Up(nDmaClients)
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val addrBits = p(PAddrBits)
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val dmaStatusBits = 2
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val dmaWordSizeBits = 2
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}
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abstract class DmaModule(implicit val p: Parameters) extends Module with HasDmaParameters
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abstract class DmaBundle(implicit val p: Parameters) extends ParameterizedBundle()(p) with HasDmaParameters
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class DmaRequest(implicit p: Parameters) extends DmaBundle()(p) {
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val xact_id = UInt(width = dmaXactIdBits)
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val client_id = UInt(width = dmaClientIdBits)
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val cmd = UInt(width = DmaRequest.DMA_CMD_SZ)
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val source = UInt(width = addrBits)
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val dest = UInt(width = addrBits)
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val length = UInt(width = addrBits)
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val size = UInt(width = dmaWordSizeBits)
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}
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class DmaResponse(implicit p: Parameters) extends DmaBundle()(p) {
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val xact_id = UInt(width = dmaXactIdBits)
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val client_id = UInt(width = dmaClientIdBits)
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val status = UInt(width = dmaStatusBits)
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}
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object DmaRequest {
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val DMA_CMD_SZ = 3
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val DMA_CMD_COPY = UInt("b000")
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val DMA_CMD_PFR = UInt("b010")
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val DMA_CMD_PFW = UInt("b011")
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val DMA_CMD_SIN = UInt("b100")
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val DMA_CMD_SOUT = UInt("b101")
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def apply(xact_id: UInt = UInt(0),
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client_id: UInt,
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cmd: UInt,
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source: UInt,
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dest: UInt,
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length: UInt,
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size: UInt = UInt(0))(implicit p: Parameters): DmaRequest = {
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val req = Wire(new DmaRequest)
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req.xact_id := xact_id
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req.client_id := client_id
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req.cmd := cmd
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req.source := source
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req.dest := dest
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req.length := length
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req.size := size
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req
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}
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}
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import DmaRequest._
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class DmaIO(implicit p: Parameters) extends DmaBundle()(p) {
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val req = Decoupled(new DmaRequest)
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val resp = Decoupled(new DmaResponse).flip
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}
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class DmaTrackerIO(implicit p: Parameters) extends DmaBundle()(p) {
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val dma = (new DmaIO).flip
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val mem = new ClientUncachedTileLinkIO
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val mmio = new NastiIO
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}
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class DmaManager(outstandingCSR: Int)(implicit p: Parameters)
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extends DmaModule()(p)
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with HasNastiParameters
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with HasAddrMapParameters {
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val io = new Bundle {
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val ctrl = (new NastiIO).flip
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val mmio = new NastiIO
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val dma = new DmaIO
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}
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private val wordBits = 1 << log2Up(addrBits)
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private val wordBytes = wordBits / 8
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private val wordOff = log2Up(wordBytes)
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private val wordMSB = wordOff + 2
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val s_idle :: s_wdata :: s_dma_req :: s_wresp :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_idle)
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val nCtrlWords = (addrBits * 4) / nastiXDataBits
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val ctrl_regs = Reg(Vec(nCtrlWords, UInt(width = nastiXDataBits)))
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val ctrl_idx = Reg(UInt(width = log2Up(nCtrlWords)))
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val ctrl_done = Reg(Bool())
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val ctrl_blob = ctrl_regs.asUInt
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val ctrl_id = Reg(UInt(width = nastiXIdBits))
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val sizeOffset = 3 * addrBits
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val cmdOffset = sizeOffset + dmaWordSizeBits
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val dma_req = new DmaRequest().fromBits(ctrl_blob)
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val dma_busy = Reg(init = UInt(0, nDmaXacts))
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val dma_xact_id = PriorityEncoder(~dma_busy)
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when (io.ctrl.aw.fire()) {
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ctrl_id := io.ctrl.aw.bits.id
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ctrl_idx := UInt(0)
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ctrl_done := Bool(false)
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state := s_wdata
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}
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when (io.ctrl.w.fire()) {
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when (!ctrl_done) {
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ctrl_regs(ctrl_idx) := io.ctrl.w.bits.data
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ctrl_idx := ctrl_idx + UInt(1)
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}
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when (ctrl_idx === UInt(nCtrlWords - 1)) { ctrl_done := Bool(true) }
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when (io.ctrl.w.bits.last) { state := s_dma_req }
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}
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dma_busy := (dma_busy |
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Mux(io.dma.req.fire(), UIntToOH(dma_xact_id), UInt(0))) &
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~Mux(io.dma.resp.fire(), UIntToOH(io.dma.resp.bits.xact_id), UInt(0))
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when (io.dma.req.fire()) { state := s_wresp }
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when (io.ctrl.b.fire()) { state := s_idle }
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io.ctrl.ar.ready := Bool(false)
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io.ctrl.aw.ready := (state === s_idle)
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io.ctrl.w.ready := (state === s_wdata)
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io.ctrl.r.valid := Bool(false)
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io.ctrl.b.valid := (state === s_wresp)
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io.ctrl.b.bits := NastiWriteResponseChannel(id = ctrl_id)
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io.dma.req.valid := (state === s_dma_req) && !dma_busy.andR
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io.dma.req.bits := dma_req
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io.dma.req.bits.xact_id := dma_xact_id
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val resp_waddr_pending = Reg(init = Bool(false))
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val resp_wdata_pending = Reg(init = Bool(false))
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val resp_wresp_pending = Reg(init = Bool(false))
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val resp_pending = resp_waddr_pending || resp_wdata_pending || resp_wresp_pending
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val resp_client_id = Reg(UInt(width = dmaClientIdBits))
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val resp_status = Reg(UInt(width = dmaStatusBits))
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io.dma.resp.ready := !resp_pending
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when (io.dma.resp.fire()) {
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resp_client_id := io.dma.resp.bits.client_id
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resp_status := io.dma.resp.bits.status
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resp_waddr_pending := Bool(true)
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resp_wdata_pending := Bool(true)
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resp_wresp_pending := Bool(true)
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}
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val addrTable = Vec.tabulate(nDmaClients) { i =>
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//UInt(addrMap(s"conf:csr$i").start + outstandingCSR * csrDataBytes)
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require(false, "CSR MMIO ports no longer exist")
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UInt(0)
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}
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io.mmio.ar.valid := Bool(false)
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io.mmio.aw.valid := resp_waddr_pending
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io.mmio.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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addr = addrTable(resp_client_id),
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size = { require(false, "CSR MMIO ports no longer exist"); UInt(0) })
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io.mmio.w.valid := resp_wdata_pending
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io.mmio.w.bits := NastiWriteDataChannel(data = resp_status)
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io.mmio.b.ready := resp_wresp_pending
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io.mmio.r.ready := Bool(false)
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when (io.mmio.aw.fire()) { resp_waddr_pending := Bool(false) }
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when (io.mmio.w.fire()) { resp_wdata_pending := Bool(false) }
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when (io.mmio.b.fire()) { resp_wresp_pending := Bool(false) }
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}
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class DmaEngine(outstandingCSR: Int)(implicit p: Parameters) extends DmaModule()(p) {
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val io = new Bundle {
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val ctrl = (new NastiIO).flip
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val mem = new ClientUncachedTileLinkIO
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val mmio = new NastiIO
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}
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val manager = Module(new DmaManager(outstandingCSR))
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val trackers = Module(new DmaTrackerFile)
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manager.io.ctrl <> io.ctrl
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trackers.io.dma <> manager.io.dma
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val innerIOs = trackers.io.mem
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val outerIOs = trackers.io.mmio :+ manager.io.mmio
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val innerArb = Module(new ClientUncachedTileLinkIOArbiter(innerIOs.size))
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innerArb.io.in <> innerIOs
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io.mem <> innerArb.io.out
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val outerArb = Module(new NastiArbiter(outerIOs.size))
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outerArb.io.master <> outerIOs
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io.mmio <> outerArb.io.slave
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assert(!io.mmio.b.valid || io.mmio.b.bits.resp === UInt(0),
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"DmaEngine: NASTI write response error")
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assert(!io.mmio.r.valid || io.mmio.r.bits.resp === UInt(0),
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"DmaEngine: NASTI read response error")
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}
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class DmaTrackerFile(implicit p: Parameters) extends DmaModule()(p) {
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val io = new Bundle {
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val dma = (new DmaIO).flip
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val mem = Vec(nDmaTransactors, new ClientUncachedTileLinkIO)
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val mmio = Vec(nDmaTransactors, new NastiIO)
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}
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val trackers = List.fill(nDmaTransactors) { Module(new DmaTracker) }
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val reqReadys = trackers.map(_.io.dma.req.ready).asUInt
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io.mem <> trackers.map(_.io.mem)
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io.mmio <> trackers.map(_.io.mmio)
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if (nDmaTransactors > 1) {
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val resp_arb = Module(new RRArbiter(new DmaResponse, nDmaTransactors))
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resp_arb.io.in <> trackers.map(_.io.dma.resp)
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io.dma.resp <> resp_arb.io.out
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val selection = PriorityEncoder(reqReadys)
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trackers.zipWithIndex.foreach { case (tracker, i) =>
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tracker.io.dma.req.valid := io.dma.req.valid && selection === UInt(i)
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tracker.io.dma.req.bits := io.dma.req.bits
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}
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io.dma.req.ready := reqReadys.orR
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} else {
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io.dma <> trackers.head.io.dma
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}
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}
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class DmaTracker(implicit p: Parameters) extends DmaModule()(p)
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with HasTileLinkParameters with HasNastiParameters {
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val io = new DmaTrackerIO
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private val blockOffset = tlBeatAddrBits + tlByteAddrBits
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private val blockBytes = tlDataBeats * tlDataBytes
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val data_buffer = Reg(Vec(2 * tlDataBeats, Bits(width = tlDataBits)))
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val get_inflight = Reg(UInt(2 * tlDataBeats))
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val put_inflight = Reg(Bool())
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val put_half = Reg(UInt(width = 1))
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val get_half = Reg(UInt(width = 1))
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val prefetch_put = Reg(Bool())
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val get_done = !get_inflight.orR
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val src_block = Reg(UInt(width = tlBlockAddrBits))
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val dst_block = Reg(UInt(width = tlBlockAddrBits))
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val offset = Reg(UInt(width = blockOffset))
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val alignment = Reg(UInt(width = blockOffset))
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val shift_dir = Reg(Bool())
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val bytes_left = Reg(UInt(width = addrBits))
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val streaming = Reg(Bool())
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val stream_addr = Reg(UInt(width = nastiXAddrBits))
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val stream_len = Reg(UInt(width = nastiXLenBits))
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val stream_size = Reg(UInt(width = nastiXSizeBits))
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val stream_idx = Reg(UInt(width = blockOffset))
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val stream_bytesel = MuxLookup(stream_size, UInt("b11111111"), Seq(
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UInt("b00") -> UInt("b00000001"),
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UInt("b01") -> UInt("b00000011"),
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UInt("b10") -> UInt("b00001111")))
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val stream_mask = FillInterleaved(8, stream_bytesel)
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val stream_last = Reg(Bool())
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val stream_word_bytes = UInt(1) << stream_size
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val stream_beat_idx = stream_idx(blockOffset - 1, tlByteAddrBits)
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val stream_byte_idx = stream_idx(tlByteAddrBits - 1, 0)
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val stream_bitshift = Cat(stream_byte_idx, UInt(0, 3))
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val stream_in_beat =
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(((io.mmio.r.bits.data & stream_mask) << stream_bitshift)) |
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(data_buffer(stream_beat_idx) & ~(stream_mask << stream_bitshift))
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val stream_out_word = data_buffer(stream_beat_idx) >> stream_bitshift
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val stream_out_last = bytes_left === stream_word_bytes
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val acq = io.mem.acquire.bits
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val gnt = io.mem.grant.bits
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val (s_idle :: s_get :: s_put :: s_prefetch ::
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s_stream_read_req :: s_stream_read_resp ::
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s_stream_write_req :: s_stream_write_data :: s_stream_write_resp ::
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s_wait :: s_resp :: Nil) = Enum(Bits(), 11)
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val state = Reg(init = s_idle)
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val (put_beat, put_done) = Counter(
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io.mem.acquire.fire() && acq.hasData(), tlDataBeats)
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val put_mask = Seq.tabulate(tlDataBytes) { i =>
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val byte_index = Cat(put_beat, UInt(i, tlByteAddrBits))
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byte_index >= offset && byte_index < bytes_left
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}.asUInt
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val prefetch_sent = io.mem.acquire.fire() && io.mem.acquire.bits.isPrefetch()
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val prefetch_busy = Reg(init = UInt(0, tlMaxClientXacts))
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val (prefetch_id, _) = Counter(prefetch_sent, tlMaxClientXacts)
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val base_index = Cat(put_half, put_beat)
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val put_data = Wire(init = Bits(0, tlDataBits))
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val beat_align = alignment(blockOffset - 1, tlByteAddrBits)
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val bit_align = Cat(alignment(tlByteAddrBits - 1, 0), UInt(0, 3))
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val rev_align = UInt(tlDataBits) - bit_align
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def getBit(value: UInt, sel: UInt): Bool =
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(value >> sel)(0)
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when (alignment === UInt(0)) {
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put_data := data_buffer(base_index)
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} .elsewhen (shift_dir) {
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val shift_index = base_index - beat_align
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when (bit_align === UInt(0)) {
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put_data := data_buffer(shift_index)
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} .otherwise {
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val upper_bits = data_buffer(shift_index)
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val lower_bits = data_buffer(shift_index - UInt(1))
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val upper_shifted = upper_bits << bit_align
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val lower_shifted = lower_bits >> rev_align
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put_data := upper_shifted | lower_shifted
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}
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} .otherwise {
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val shift_index = base_index + beat_align
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when (bit_align === UInt(0)) {
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put_data := data_buffer(shift_index)
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} .otherwise {
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val upper_bits = data_buffer(shift_index + UInt(1))
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val lower_bits = data_buffer(shift_index)
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val upper_shifted = upper_bits << rev_align
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val lower_shifted = lower_bits >> bit_align
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put_data := upper_shifted | lower_shifted
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}
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}
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val put_acquire = PutBlock(
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client_xact_id = UInt(2),
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addr_block = dst_block,
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addr_beat = put_beat,
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data = put_data,
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wmask = Some(put_mask))
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val get_acquire = GetBlock(
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client_xact_id = get_half,
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addr_block = src_block,
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alloc = Bool(false))
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val prefetch_acquire = Mux(prefetch_put,
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PutPrefetch(client_xact_id = prefetch_id, addr_block = dst_block),
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GetPrefetch(client_xact_id = prefetch_id, addr_block = dst_block))
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val resp_xact_id = Reg(UInt(width = dmaXactIdBits))
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val resp_client_id = Reg(UInt(width = dmaClientIdBits))
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io.mem.acquire.valid := (state === s_get) ||
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(state === s_put && get_done) ||
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(state === s_prefetch && !prefetch_busy(prefetch_id))
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io.mem.acquire.bits := MuxLookup(
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state, prefetch_acquire, Seq(
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s_get -> get_acquire,
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s_put -> put_acquire))
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io.mem.grant.ready := Bool(true)
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io.dma.req.ready := state === s_idle
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io.dma.resp.valid := state === s_resp
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io.dma.resp.bits.xact_id := resp_xact_id
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io.dma.resp.bits.client_id := resp_client_id
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io.dma.resp.bits.status := UInt(0)
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io.mmio.ar.valid := (state === s_stream_read_req)
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io.mmio.ar.bits := NastiReadAddressChannel(
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id = UInt(0),
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addr = stream_addr,
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size = stream_size,
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len = stream_len,
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burst = BURST_FIXED)
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io.mmio.r.ready := (state === s_stream_read_resp)
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io.mmio.aw.valid := (state === s_stream_write_req)
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io.mmio.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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addr = stream_addr,
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size = stream_size,
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len = stream_len,
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burst = BURST_FIXED)
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io.mmio.w.valid := (state === s_stream_write_data) && get_done
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io.mmio.w.bits := NastiWriteDataChannel(
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data = stream_out_word,
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last = stream_out_last)
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io.mmio.b.ready := (state === s_stream_write_resp)
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when (io.dma.req.fire()) {
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val src_off = io.dma.req.bits.source(blockOffset - 1, 0)
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val dst_off = io.dma.req.bits.dest(blockOffset - 1, 0)
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val direction = src_off < dst_off
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resp_xact_id := io.dma.req.bits.xact_id
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resp_client_id := io.dma.req.bits.client_id
|
||||
src_block := io.dma.req.bits.source(addrBits - 1, blockOffset)
|
||||
dst_block := io.dma.req.bits.dest(addrBits - 1, blockOffset)
|
||||
alignment := Mux(direction, dst_off - src_off, src_off - dst_off)
|
||||
shift_dir := direction
|
||||
offset := dst_off
|
||||
bytes_left := io.dma.req.bits.length + dst_off
|
||||
get_inflight := UInt(0)
|
||||
put_inflight := Bool(false)
|
||||
get_half := UInt(0)
|
||||
put_half := UInt(0)
|
||||
streaming := Bool(false)
|
||||
stream_len := (io.dma.req.bits.length >> io.dma.req.bits.size) - UInt(1)
|
||||
stream_size := io.dma.req.bits.size
|
||||
stream_last := Bool(false)
|
||||
|
||||
when (io.dma.req.bits.cmd === DMA_CMD_COPY) {
|
||||
state := s_get
|
||||
} .elsewhen (io.dma.req.bits.cmd(2, 1) === UInt("b01")) {
|
||||
prefetch_put := io.dma.req.bits.cmd(0)
|
||||
state := s_prefetch
|
||||
} .elsewhen (io.dma.req.bits.cmd === DMA_CMD_SIN) {
|
||||
stream_addr := io.dma.req.bits.source
|
||||
stream_idx := dst_off
|
||||
streaming := Bool(true)
|
||||
alignment := UInt(0)
|
||||
state := s_stream_read_req
|
||||
} .elsewhen (io.dma.req.bits.cmd === DMA_CMD_SOUT) {
|
||||
stream_addr := io.dma.req.bits.dest
|
||||
stream_idx := src_off
|
||||
streaming := Bool(true)
|
||||
bytes_left := io.dma.req.bits.length
|
||||
state := s_stream_write_req
|
||||
}
|
||||
}
|
||||
|
||||
when (io.mmio.ar.fire()) { state := s_stream_read_resp }
|
||||
|
||||
when (io.mmio.r.fire()) {
|
||||
data_buffer(stream_beat_idx) := stream_in_beat
|
||||
stream_idx := stream_idx + stream_word_bytes
|
||||
val block_finished = stream_idx === UInt(blockBytes) - stream_word_bytes
|
||||
when (block_finished || io.mmio.r.bits.last) { state := s_put }
|
||||
}
|
||||
|
||||
when (io.mmio.aw.fire()) { state := s_get }
|
||||
|
||||
when (io.mmio.w.fire()) {
|
||||
stream_idx := stream_idx + stream_word_bytes
|
||||
bytes_left := bytes_left - stream_word_bytes
|
||||
val block_finished = stream_idx === UInt(blockBytes) - stream_word_bytes
|
||||
when (stream_out_last) {
|
||||
state := s_stream_write_resp
|
||||
} .elsewhen (block_finished) {
|
||||
state := s_get
|
||||
}
|
||||
}
|
||||
|
||||
when (io.mmio.b.fire()) { state := s_resp }
|
||||
|
||||
when (state === s_get && io.mem.acquire.ready) {
|
||||
get_inflight := get_inflight | FillInterleaved(tlDataBeats, UIntToOH(get_half))
|
||||
src_block := src_block + UInt(1)
|
||||
when (streaming) {
|
||||
state := s_stream_write_data
|
||||
} .otherwise {
|
||||
val bytes_in_buffer = UInt(blockBytes) - alignment
|
||||
val extra_read = alignment > UInt(0) && !shift_dir && // dst_off < src_off
|
||||
get_half === UInt(0) && // this is the first block
|
||||
bytes_in_buffer < bytes_left // there is still more data left to fetch
|
||||
get_half := get_half + UInt(1)
|
||||
when (!extra_read) { state := s_put }
|
||||
}
|
||||
}
|
||||
|
||||
when (prefetch_sent) {
|
||||
prefetch_busy := prefetch_busy | UIntToOH(prefetch_id)
|
||||
when (bytes_left < UInt(blockBytes)) {
|
||||
bytes_left := UInt(0)
|
||||
state := s_resp
|
||||
} .otherwise {
|
||||
bytes_left := bytes_left - UInt(blockBytes)
|
||||
dst_block := dst_block + UInt(1)
|
||||
}
|
||||
}
|
||||
|
||||
when (io.mem.grant.fire()) {
|
||||
when (gnt.g_type === Grant.prefetchAckType) {
|
||||
prefetch_busy := prefetch_busy & ~UIntToOH(gnt.client_xact_id)
|
||||
} .elsewhen (gnt.hasData()) {
|
||||
val write_half = gnt.client_xact_id(0)
|
||||
val write_idx = Cat(write_half, gnt.addr_beat)
|
||||
get_inflight := get_inflight & ~UIntToOH(write_idx)
|
||||
data_buffer(write_idx) := gnt.data
|
||||
} .otherwise {
|
||||
put_inflight := Bool(false)
|
||||
}
|
||||
}
|
||||
|
||||
when (put_done) { // state === s_put
|
||||
when (!streaming) {
|
||||
put_half := put_half + UInt(1)
|
||||
}
|
||||
offset := UInt(0)
|
||||
stream_idx := UInt(0)
|
||||
when (bytes_left < UInt(blockBytes)) {
|
||||
bytes_left := UInt(0)
|
||||
} .otherwise {
|
||||
bytes_left := bytes_left - UInt(blockBytes)
|
||||
}
|
||||
put_inflight := Bool(true)
|
||||
dst_block := dst_block + UInt(1)
|
||||
state := s_wait
|
||||
}
|
||||
|
||||
when (state === s_wait && get_done && !put_inflight) {
|
||||
state := MuxCase(s_get, Seq(
|
||||
(bytes_left === UInt(0)) -> s_resp,
|
||||
streaming -> s_stream_read_resp))
|
||||
}
|
||||
|
||||
when (io.dma.resp.fire()) { state := s_idle }
|
||||
}
|
||||
Reference in New Issue
Block a user