riscv/rocket-chip
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strip DMA and RoCC CSRs out of rocket and uncore (#201)

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This commit is contained in:
Howard Mao
2016-08-15 23:08:55 -07:00
committed by Andrew Waterman
parent 47a0c880a4
commit 38e0967816
9 changed files with 1 additions and 977 deletions
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15
rocket/src/main/scala/tile.scala
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@ -18,7 +18,6 @@ case class RoccParameters(
generator: Parameters => RoCC,
nMemChannels: Int = 0,
nPTWPorts : Int = 0,
csrs: Seq[Int] = Nil,
useFPU: Boolean = false)
abstract class Tile(clockSignal: Clock = null, resetSignal: Bool = null)
@ -70,12 +69,10 @@ class RocketTile(clockSignal: Clock = null, resetSignal: Bool = null)
val rocc = accelParams.generator(p.alterPartial({
case RoccNMemChannels => accelParams.nMemChannels
case RoccNPTWPorts => accelParams.nPTWPorts
case RoccNCSRs => accelParams.csrs.size
}))
val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams))
rocc.io.cmd <> cmdRouter.io.out(i)
rocc.io.exception := core.io.rocc.exception
rocc.io.host_id := io.prci.id
dcIF.io.requestor <> rocc.io.mem
dcPorts += dcIF.io.cache
uncachedArbPorts += rocc.io.autl
@ -101,18 +98,6 @@ class RocketTile(clockSignal: Clock = null, resetSignal: Bool = null)
core.io.rocc.interrupt := roccs.map(_.io.interrupt).reduce(_ || _)
respArb.io.in <> roccs.map(rocc => Queue(rocc.io.resp))
if (p(RoccNCSRs) > 0) {
core.io.rocc.csr.rdata <> roccs.flatMap(_.io.csr.rdata)
for ((rocc, accelParams) <- roccs.zip(buildRocc)) {
rocc.io.csr.waddr := core.io.rocc.csr.waddr
rocc.io.csr.wdata := core.io.rocc.csr.wdata
rocc.io.csr.wen := core.io.rocc.csr.wen &&
accelParams.csrs
.map(core.io.rocc.csr.waddr === UInt(_))
.reduce((a, b) => a || b)
}
}
ptwPorts ++= roccs.flatMap(_.io.ptw)
uncachedPorts ++= roccs.flatMap(_.io.utl)
}