riscv/rocket-chip
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strip DMA and RoCC CSRs out of rocket and uncore (#201)

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This commit is contained in:
Howard Mao
2016-08-15 23:08:55 -07:00
committed by Andrew Waterman
parent 47a0c880a4
commit 38e0967816
9 changed files with 1 additions and 977 deletions
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9
rocket/src/main/scala/csr.scala
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@ -332,11 +332,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
read_mapping += addr -> io.custom_mrw_csrs(i)
}
for ((addr, i) <- roccCsrs.zipWithIndex) {
require(!read_mapping.contains(addr), "RoCC: CSR address " + addr + " is already in use")
read_mapping += addr -> io.rocc.csr.rdata(i)
}
val decoded_addr = read_mapping map { case (k, v) => k -> (io.rw.addr === k) }
val addr_valid = decoded_addr.values.reduce(_||_)
@ -559,10 +554,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
reg_dcsr.debugint := io.prci.interrupts.debug
reg_dcsr.hwbpcount := UInt(p(NBreakpoints))
io.rocc.csr.waddr := io.rw.addr
io.rocc.csr.wdata := wdata
io.rocc.csr.wen := wen
if (!usingUser) {
reg_mstatus.mpp := PRV.M
reg_mstatus.prv := PRV.M