strip DMA and RoCC CSRs out of rocket and uncore (#201)
This commit is contained in:
Howard Mao
committed by
Andrew Waterman
Andrew Waterman
parent
47a0c880a4
commit
38e0967816
@ -332,11 +332,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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read_mapping += addr -> io.custom_mrw_csrs(i)
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}
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for ((addr, i) <- roccCsrs.zipWithIndex) {
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require(!read_mapping.contains(addr), "RoCC: CSR address " + addr + " is already in use")
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read_mapping += addr -> io.rocc.csr.rdata(i)
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}
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val decoded_addr = read_mapping map { case (k, v) => k -> (io.rw.addr === k) }
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val addr_valid = decoded_addr.values.reduce(_||_)
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@ -559,10 +554,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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reg_dcsr.debugint := io.prci.interrupts.debug
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reg_dcsr.hwbpcount := UInt(p(NBreakpoints))
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io.rocc.csr.waddr := io.rw.addr
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io.rocc.csr.wdata := wdata
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io.rocc.csr.wen := wen
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if (!usingUser) {
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reg_mstatus.mpp := PRV.M
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reg_mstatus.prv := PRV.M
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@ -1,400 +0,0 @@
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package rocket
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import Chisel._
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import uncore.tilelink._
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import uncore.devices._
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import uncore.devices.DmaRequest._
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import uncore.agents._
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import uncore.util._
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import junctions.{ParameterizedBundle, AddrMap}
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import cde.Parameters
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trait HasClientDmaParameters extends HasCoreParameters with HasDmaParameters {
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val dmaAddrBits = coreMaxAddrBits
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val dmaSegmentSizeBits = coreMaxAddrBits
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val dmaSegmentBits = 24
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}
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abstract class ClientDmaBundle(implicit val p: Parameters)
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extends ParameterizedBundle()(p) with HasClientDmaParameters
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abstract class ClientDmaModule(implicit val p: Parameters)
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extends Module with HasClientDmaParameters
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class ClientDmaRequest(implicit p: Parameters) extends ClientDmaBundle()(p) {
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val cmd = UInt(width = DMA_CMD_SZ)
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val src_start = UInt(width = dmaAddrBits)
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val dst_start = UInt(width = dmaAddrBits)
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val src_stride = UInt(width = dmaSegmentSizeBits)
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val dst_stride = UInt(width = dmaSegmentSizeBits)
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val segment_size = UInt(width = dmaSegmentSizeBits)
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val nsegments = UInt(width = dmaSegmentBits)
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val word_size = UInt(width = dmaWordSizeBits)
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}
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object ClientDmaRequest {
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def apply(cmd: UInt,
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src_start: UInt,
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dst_start: UInt,
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segment_size: UInt,
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nsegments: UInt = UInt(1),
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src_stride: UInt = UInt(0),
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dst_stride: UInt = UInt(0),
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word_size: UInt = UInt(0))
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(implicit p: Parameters) = {
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val req = Wire(new ClientDmaRequest)
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req.cmd := cmd
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req.src_start := src_start
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req.dst_start := dst_start
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req.src_stride := src_stride
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req.dst_stride := dst_stride
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req.segment_size := segment_size
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req.nsegments := nsegments
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req.word_size := word_size
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req
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}
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}
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object ClientDmaResponse {
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val pagefault = UInt("b01")
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val invalid_region = UInt("b10")
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def apply(status: UInt = UInt(0))(implicit p: Parameters) = {
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val resp = Wire(new ClientDmaResponse)
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resp.status := status
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resp
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}
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}
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class ClientDmaResponse(implicit p: Parameters) extends ClientDmaBundle {
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val status = UInt(width = dmaStatusBits)
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}
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class ClientDmaIO(implicit p: Parameters) extends ParameterizedBundle()(p) {
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val req = Decoupled(new ClientDmaRequest)
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val resp = Valid(new ClientDmaResponse).flip
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}
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class DmaFrontend(implicit p: Parameters) extends CoreModule()(p)
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with HasClientDmaParameters with HasTileLinkParameters {
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val io = new Bundle {
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val cpu = (new ClientDmaIO).flip
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val mem = new ClientUncachedTileLinkIO
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val ptw = new TLBPTWIO
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val busy = Bool(OUTPUT)
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val incr_outstanding = Bool(OUTPUT)
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val host_id = UInt(INPUT, log2Up(nCores))
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}
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val tlb = Module(new DecoupledTLB()(p.alterPartial({
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case CacheName => "L1D"
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})))
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io.ptw <> tlb.io.ptw
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private val pgSize = 1 << pgIdxBits
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val cmd = Reg(UInt(width = DMA_CMD_SZ))
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val adv_ptr = MuxLookup(cmd, UInt("b11"), Seq(
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DMA_CMD_PFR -> UInt("b10"),
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DMA_CMD_PFW -> UInt("b10"),
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DMA_CMD_SIN -> UInt("b10"),
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DMA_CMD_SOUT -> UInt("b01")))
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val segment_size = Reg(UInt(width = dmaSegmentSizeBits))
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val bytes_left = Reg(UInt(width = dmaSegmentSizeBits))
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val segments_left = Reg(UInt(width = dmaSegmentBits))
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val word_size = Reg(UInt(width = dmaWordSizeBits))
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val src_vaddr = Reg(UInt(width = dmaAddrBits))
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val dst_vaddr = Reg(UInt(width = dmaAddrBits))
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val src_vpn = src_vaddr(dmaAddrBits - 1, pgIdxBits)
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val dst_vpn = dst_vaddr(dmaAddrBits - 1, pgIdxBits)
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val src_idx = src_vaddr(pgIdxBits - 1, 0)
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val dst_idx = dst_vaddr(pgIdxBits - 1, 0)
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val src_pglen = UInt(pgSize) - src_idx
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val dst_pglen = UInt(pgSize) - dst_idx
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val src_stride = Reg(UInt(width = dmaSegmentSizeBits))
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val dst_stride = Reg(UInt(width = dmaSegmentSizeBits))
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val src_ppn = Reg(UInt(width = ppnBits))
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val dst_ppn = Reg(UInt(width = ppnBits))
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val src_paddr = Cat(src_ppn, src_idx)
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val dst_paddr = Cat(dst_ppn, dst_idx)
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val last_src_vpn = Reg(UInt(width = vpnBits))
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val last_dst_vpn = Reg(UInt(width = vpnBits))
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val tx_len = src_pglen min dst_pglen min bytes_left
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val dma_busy = Reg(init = UInt(0, tlMaxClientXacts))
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val dma_xact_id = PriorityEncoder(~dma_busy)
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val (dma_req_beat, dma_req_done) = Counter(io.mem.acquire.fire(), tlDataBeats)
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val (s_idle :: s_translate :: s_dma_req :: s_dma_update ::
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s_prepare :: s_finish :: Nil) = Enum(Bits(), 6)
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val state = Reg(init = s_idle)
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// lower bit is for src, higher bit is for dst
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val to_translate = Reg(init = UInt(0, 2))
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val tlb_sent = Reg(init = UInt(0, 2))
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val tlb_to_send = to_translate & ~tlb_sent
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val resp_status = Reg(UInt(width = dmaStatusBits))
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def make_acquire(
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addr_beat: UInt, client_xact_id: UInt, client_id: UInt,
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cmd: UInt, source: UInt, dest: UInt,
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length: UInt, size: UInt): Acquire = {
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val data_blob = Wire(UInt(width = tlDataBeats * tlDataBits))
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data_blob := DmaRequest(
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xact_id = UInt(0),
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client_id = client_id,
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cmd = cmd,
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source = source,
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dest = dest,
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length = length,
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size = size).asUInt
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val data_beats = Vec(tlDataBeats, UInt(width = tlDataBits)).fromBits(data_blob)
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val base_addr = addrMap("devices:dma").start
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val addr_block = UInt(base_addr >> (tlBeatAddrBits + tlByteAddrBits))
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PutBlock(
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client_xact_id = client_xact_id,
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addr_block = addr_block,
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addr_beat = addr_beat,
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data = data_beats(addr_beat),
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alloc = Bool(false))
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}
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def check_region(cmd: UInt, src: UInt, dst: UInt): Bool = {
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val src_cacheable = addrMap.isCacheable(src)
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val dst_cacheable = addrMap.isCacheable(dst)
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val dst_ok = Mux(cmd === DMA_CMD_SOUT, !dst_cacheable, dst_cacheable)
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val src_ok = Mux(cmd === DMA_CMD_SIN, !src_cacheable, Bool(true))
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dst_ok && src_ok
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}
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tlb.io.req.valid := tlb_to_send.orR
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tlb.io.req.bits.vpn := Mux(tlb_to_send(0), src_vpn, dst_vpn)
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tlb.io.req.bits.passthrough := Bool(false)
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tlb.io.req.bits.instruction := Bool(false)
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tlb.io.req.bits.store := !tlb_to_send(0)
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tlb.io.resp.ready := tlb_sent.orR
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when (tlb.io.req.fire()) {
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tlb_sent := tlb_sent | PriorityEncoderOH(tlb_to_send)
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}
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when (tlb.io.resp.fire()) {
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val recv_choice = PriorityEncoderOH(to_translate)
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val error = Mux(recv_choice(0),
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tlb.io.resp.bits.xcpt_ld, tlb.io.resp.bits.xcpt_st)
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when (error) {
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resp_status := ClientDmaResponse.pagefault
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state := s_finish
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}
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// getting the src translation
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when (recv_choice(0)) {
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src_ppn := tlb.io.resp.bits.ppn
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} .otherwise {
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dst_ppn := tlb.io.resp.bits.ppn
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}
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to_translate := to_translate & ~recv_choice
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}
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io.cpu.req.ready := state === s_idle
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io.cpu.resp.valid := state === s_finish
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io.cpu.resp.bits := ClientDmaResponse(resp_status)
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io.mem.acquire.valid := (state === s_dma_req) && !dma_busy.andR
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io.mem.acquire.bits := make_acquire(
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addr_beat = dma_req_beat,
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client_id = io.host_id,
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client_xact_id = dma_xact_id,
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cmd = cmd, source = src_paddr, dest = dst_paddr,
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length = tx_len, size = word_size)
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io.mem.grant.ready := (state =/= s_dma_req)
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when (io.cpu.req.fire()) {
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val req = io.cpu.req.bits
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val is_prefetch = req.cmd(2, 1) === UInt("b01")
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cmd := req.cmd
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src_vaddr := req.src_start
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dst_vaddr := req.dst_start
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src_stride := req.src_stride
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dst_stride := req.dst_stride
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segment_size := req.segment_size
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segments_left := req.nsegments - UInt(1)
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bytes_left := req.segment_size
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word_size := req.word_size
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to_translate := Mux(is_prefetch, UInt("b10"), UInt("b11"))
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tlb_sent := UInt(0)
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state := s_translate
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}
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when (state === s_translate && !to_translate.orR) {
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when (check_region(cmd, src_paddr, dst_paddr)) {
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state := s_dma_req
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} .otherwise {
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resp_status := ClientDmaResponse.invalid_region
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state := s_finish
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}
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}
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def setBusy(set: Bool, xact_id: UInt): UInt =
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Mux(set, UIntToOH(xact_id), UInt(0))
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dma_busy := (dma_busy |
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setBusy(dma_req_done, dma_xact_id)) &
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~setBusy(io.mem.grant.fire(), io.mem.grant.bits.client_xact_id)
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when (dma_req_done) {
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src_vaddr := src_vaddr + Mux(adv_ptr(0), tx_len, UInt(0))
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dst_vaddr := dst_vaddr + Mux(adv_ptr(1), tx_len, UInt(0))
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bytes_left := bytes_left - tx_len
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state := s_dma_update
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}
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when (state === s_dma_update) {
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when (bytes_left === UInt(0)) {
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when (segments_left === UInt(0)) {
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resp_status := UInt(0)
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state := s_finish
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} .otherwise {
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last_src_vpn := src_vpn
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last_dst_vpn := dst_vpn
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src_vaddr := src_vaddr + src_stride
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dst_vaddr := dst_vaddr + dst_stride
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bytes_left := segment_size
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segments_left := segments_left - UInt(1)
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state := s_prepare
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}
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} .otherwise {
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to_translate := adv_ptr & Cat(dst_idx === UInt(0), src_idx === UInt(0))
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tlb_sent := UInt(0)
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state := s_translate
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}
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}
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when (state === s_prepare) {
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to_translate := adv_ptr & Cat(
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dst_vpn =/= last_dst_vpn,
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src_vpn =/= last_src_vpn)
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tlb_sent := UInt(0)
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state := s_translate
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}
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when (state === s_finish) { state := s_idle }
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io.busy := (state =/= s_idle) || dma_busy.orR
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io.incr_outstanding := dma_req_done
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}
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object DmaCtrlRegNumbers {
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val SRC_STRIDE = 0
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val DST_STRIDE = 1
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val SEGMENT_SIZE = 2
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val NSEGMENTS = 3
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val WORD_SIZE = 4
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val RESP_STATUS = 5
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val OUTSTANDING = 6
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val NCSRS = 7
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val CSR_BASE = 0x800
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val CSR_END = CSR_BASE + NCSRS
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}
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import DmaCtrlRegNumbers._
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class DmaCtrlRegFile(implicit val p: Parameters) extends Module
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with HasClientDmaParameters with HasTileLinkParameters {
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private val nWriteRegs = 5
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private val nRegs = nWriteRegs + 2
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val io = new Bundle {
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val wen = Bool(INPUT)
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val waddr = UInt(INPUT, log2Up(nRegs))
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val wdata = UInt(INPUT, dmaSegmentSizeBits)
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val src_stride = UInt(OUTPUT, dmaSegmentSizeBits)
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val dst_stride = UInt(OUTPUT, dmaSegmentSizeBits)
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val segment_size = UInt(OUTPUT, dmaSegmentSizeBits)
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val nsegments = UInt(OUTPUT, dmaSegmentBits)
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val word_size = UInt(OUTPUT, dmaWordSizeBits)
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val incr_outstanding = Bool(INPUT)
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val xact_outstanding = Bool(OUTPUT)
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}
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val regs = Reg(Vec(nWriteRegs, UInt(width = dmaSegmentSizeBits)))
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val waddr = io.waddr(log2Up(NCSRS) - 1, 0)
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io.src_stride := regs(SRC_STRIDE)
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io.dst_stride := regs(DST_STRIDE)
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io.segment_size := regs(SEGMENT_SIZE)
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io.nsegments := regs(NSEGMENTS)
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io.word_size := regs(WORD_SIZE)
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when (io.wen && waddr < UInt(nWriteRegs)) {
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regs(waddr) := io.wdata
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}
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val outstanding_cnt = TwoWayCounter(
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io.incr_outstanding,
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io.wen && io.waddr === UInt(OUTSTANDING),
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tlMaxClientXacts)
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io.xact_outstanding := outstanding_cnt > UInt(0)
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}
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class DmaController(implicit p: Parameters) extends RoCC()(p)
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with HasClientDmaParameters {
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io.mem.req.valid := Bool(false)
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io.resp.valid := Bool(false)
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io.interrupt := Bool(false)
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val cmd = Queue(io.cmd)
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val inst = cmd.bits.inst
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val is_transfer = inst.funct < UInt(8)
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val reg_status = Reg(UInt(width = dmaStatusBits))
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val crfile = Module(new DmaCtrlRegFile)
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crfile.io.waddr := io.csr.waddr
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crfile.io.wdata := io.csr.wdata
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crfile.io.wen := io.csr.wen
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io.csr.rdata(SRC_STRIDE) := crfile.io.src_stride
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io.csr.rdata(DST_STRIDE) := crfile.io.dst_stride
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io.csr.rdata(SEGMENT_SIZE) := crfile.io.segment_size
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io.csr.rdata(NSEGMENTS) := crfile.io.nsegments
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io.csr.rdata(WORD_SIZE) := crfile.io.word_size
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io.csr.rdata(RESP_STATUS) := reg_status
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val frontend = Module(new DmaFrontend)
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io.ptw(0) <> frontend.io.ptw
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io.autl <> frontend.io.mem
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crfile.io.incr_outstanding := frontend.io.incr_outstanding
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frontend.io.host_id := io.host_id
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frontend.io.cpu.req.valid := cmd.valid && is_transfer
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frontend.io.cpu.req.bits := ClientDmaRequest(
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cmd = cmd.bits.inst.funct,
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src_start = cmd.bits.rs2,
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dst_start = cmd.bits.rs1,
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src_stride = crfile.io.src_stride,
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dst_stride = crfile.io.dst_stride,
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segment_size = crfile.io.segment_size,
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nsegments = crfile.io.nsegments,
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word_size = crfile.io.word_size)
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cmd.ready := is_transfer && frontend.io.cpu.req.ready
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when (frontend.io.cpu.resp.valid) {
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reg_status := frontend.io.cpu.resp.bits.status
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}
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io.busy := cmd.valid || frontend.io.busy || crfile.io.xact_outstanding
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}
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@ -12,14 +12,6 @@ import cde.{Parameters, Field}
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case object RoccMaxTaggedMemXacts extends Field[Int]
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case object RoccNMemChannels extends Field[Int]
|
||||
case object RoccNPTWPorts extends Field[Int]
|
||||
case object RoccNCSRs extends Field[Int]
|
||||
|
||||
class RoCCCSRs(implicit p: Parameters) extends CoreBundle()(p) {
|
||||
val rdata = Vec(nRoccCsrs, UInt(INPUT, xLen))
|
||||
val waddr = UInt(OUTPUT, CSR.ADDRSZ)
|
||||
val wdata = UInt(OUTPUT, xLen)
|
||||
val wen = Bool(OUTPUT)
|
||||
}
|
||||
|
||||
class RoCCInstruction extends Bundle
|
||||
{
|
||||
@ -59,8 +51,6 @@ class RoCCInterface(implicit p: Parameters) extends CoreBundle()(p) {
|
||||
val fpu_req = Decoupled(new FPInput)
|
||||
val fpu_resp = Decoupled(new FPResult).flip
|
||||
val exception = Bool(INPUT)
|
||||
val csr = (new RoCCCSRs).flip
|
||||
val host_id = UInt(INPUT, log2Up(nCores))
|
||||
|
||||
override def cloneType = new RoCCInterface().asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
@ -63,9 +63,6 @@ trait HasCoreParameters extends HasAddrMapParameters {
|
||||
val vaddrBitsExtended = vpnBitsExtended + pgIdxBits
|
||||
val coreMaxAddrBits = paddrBits max vaddrBitsExtended
|
||||
val nCustomMrwCsrs = p(NCustomMRWCSRs)
|
||||
val roccCsrs = if (p(BuildRoCC).isEmpty) Nil
|
||||
else p(BuildRoCC).flatMap(_.csrs)
|
||||
val nRoccCsrs = p(RoccNCSRs)
|
||||
val nCores = p(NTiles)
|
||||
|
||||
// fetchWidth doubled, but coreInstBytes halved, for RVC
|
||||
@ -499,7 +496,6 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
|
||||
csr.io.prci <> io.prci
|
||||
io.fpu.fcsr_rm := csr.io.fcsr_rm
|
||||
csr.io.fcsr_flags := io.fpu.fcsr_flags
|
||||
io.rocc.csr <> csr.io.rocc.csr
|
||||
csr.io.rocc.interrupt <> io.rocc.interrupt
|
||||
csr.io.pc := wb_reg_pc
|
||||
csr.io.badaddr := encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata)
|
||||
|
||||
@ -18,7 +18,6 @@ case class RoccParameters(
|
||||
generator: Parameters => RoCC,
|
||||
nMemChannels: Int = 0,
|
||||
nPTWPorts : Int = 0,
|
||||
csrs: Seq[Int] = Nil,
|
||||
useFPU: Boolean = false)
|
||||
|
||||
abstract class Tile(clockSignal: Clock = null, resetSignal: Bool = null)
|
||||
@ -70,12 +69,10 @@ class RocketTile(clockSignal: Clock = null, resetSignal: Bool = null)
|
||||
val rocc = accelParams.generator(p.alterPartial({
|
||||
case RoccNMemChannels => accelParams.nMemChannels
|
||||
case RoccNPTWPorts => accelParams.nPTWPorts
|
||||
case RoccNCSRs => accelParams.csrs.size
|
||||
}))
|
||||
val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams))
|
||||
rocc.io.cmd <> cmdRouter.io.out(i)
|
||||
rocc.io.exception := core.io.rocc.exception
|
||||
rocc.io.host_id := io.prci.id
|
||||
dcIF.io.requestor <> rocc.io.mem
|
||||
dcPorts += dcIF.io.cache
|
||||
uncachedArbPorts += rocc.io.autl
|
||||
@ -101,18 +98,6 @@ class RocketTile(clockSignal: Clock = null, resetSignal: Bool = null)
|
||||
core.io.rocc.interrupt := roccs.map(_.io.interrupt).reduce(_ || _)
|
||||
respArb.io.in <> roccs.map(rocc => Queue(rocc.io.resp))
|
||||
|
||||
if (p(RoccNCSRs) > 0) {
|
||||
core.io.rocc.csr.rdata <> roccs.flatMap(_.io.csr.rdata)
|
||||
for ((rocc, accelParams) <- roccs.zip(buildRocc)) {
|
||||
rocc.io.csr.waddr := core.io.rocc.csr.waddr
|
||||
rocc.io.csr.wdata := core.io.rocc.csr.wdata
|
||||
rocc.io.csr.wen := core.io.rocc.csr.wen &&
|
||||
accelParams.csrs
|
||||
.map(core.io.rocc.csr.waddr === UInt(_))
|
||||
.reduce((a, b) => a || b)
|
||||
}
|
||||
}
|
||||
|
||||
ptwPorts ++= roccs.flatMap(_.io.ptw)
|
||||
uncachedPorts ++= roccs.flatMap(_.io.utl)
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user