riscv/rocket-chip
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strip DMA and RoCC CSRs out of rocket and uncore (#201)

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Howard Mao authored and Andrew Waterman committed 2016-08-15 23:08:55 -07:00
1 parent 47a0c880a4
commit 38e0967816
9 files changed
+1 -977
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groundtest/src/main/scala/Tile.scala
+1 -2
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@@ -11,8 +11,7 @@ import cde.{Parameters, Field}
case object BuildGroundTest extends Field[Parameters => GroundTest]
case class GroundTestTileSettings(
uncached: Int = 0, cached: Int = 0, ptw: Int = 0,
maxXacts: Int = 1, csrs: Int = 0)
uncached: Int = 0, cached: Int = 0, ptw: Int = 0, maxXacts: Int = 1)
case object GroundTestKey extends Field[Seq[GroundTestTileSettings]]
case object GroundTestId extends Field[Int]