riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

strip DMA and RoCC CSRs out of rocket and uncore (#201)

Browse Source
This commit is contained in:
Howard Mao
2016-08-15 23:08:55 -07:00
committed by Andrew Waterman
parent 47a0c880a4
commit 38e0967816
9 changed files with 1 additions and 977 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
coreplex/src/main/scala/Configs.scala
View File

@ -101,7 +101,6 @@ class BaseCoreplexConfig extends Config (
case BuildRoCC => Nil
case RoccNMemChannels => site(BuildRoCC).map(_.nMemChannels).foldLeft(0)(_ + _)
case RoccNPTWPorts => site(BuildRoCC).map(_.nPTWPorts).foldLeft(0)(_ + _)
case RoccNCSRs => site(BuildRoCC).map(_.csrs.size).foldLeft(0)(_ + _)
//Rocket Core Constants
case FetchWidth => if (site(UseCompressed)) 2 else 1
case RetireWidth => 1

1
coreplex/src/main/scala/TestConfigs.scala
View File

@ -49,7 +49,6 @@ class WithGroundTest extends Config(
case GroundTestId => i
case NCachedTileLinkPorts => if(tileSettings.cached > 0) 1 else 0
case NUncachedTileLinkPorts => tileSettings.uncached
case RoccNCSRs => tileSettings.csrs
})))
}
}