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tilelink2 axi4: RegisterRouter can cut ready dependency

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This commit is contained in:
Wesley W. Terpstra
2016-10-11 22:24:06 -07:00
parent dc26736f32
commit 38b6c1c820
2 changed files with 2 additions and 2 deletions
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2
src/main/scala/uncore/axi4/RegisterRouter.scala
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@@ -49,7 +49,7 @@ class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int
// Invoke the register map builder and make it Irrevocable // Invoke the register map builder and make it Irrevocable
val out = Queue.irrevocable( val out = Queue.irrevocable(
RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*), RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*),
entries = 1, pipe = true, flow = true) entries = 1, flow = true)
// No flow control needed // No flow control needed
out.ready := Mux(out.bits.read, r.ready, b.ready) out.ready := Mux(out.bits.read, r.ready, b.ready)

2
src/main/scala/uncore/tilelink2/RegisterRouter.scala
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@@ -44,7 +44,7 @@ class TLRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int =
// Invoke the register map builder and make it Irrevocable // Invoke the register map builder and make it Irrevocable
val out = Queue.irrevocable( val out = Queue.irrevocable(
RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*), RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*),
entries = 1, pipe = true, flow = true) entries = 1, flow = true)
// No flow control needed // No flow control needed
in.valid := a.valid in.valid := a.valid