From 38b6c1c820969a03e718ddfca89a4c6b20bc5ef4 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Tue, 11 Oct 2016 22:24:06 -0700 Subject: [PATCH] tilelink2 axi4: RegisterRouter can cut ready dependency --- src/main/scala/uncore/axi4/RegisterRouter.scala | 2 +- src/main/scala/uncore/tilelink2/RegisterRouter.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/uncore/axi4/RegisterRouter.scala b/src/main/scala/uncore/axi4/RegisterRouter.scala index b46d69f0..97b598d5 100644 --- a/src/main/scala/uncore/axi4/RegisterRouter.scala +++ b/src/main/scala/uncore/axi4/RegisterRouter.scala @@ -49,7 +49,7 @@ class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int // Invoke the register map builder and make it Irrevocable val out = Queue.irrevocable( RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*), - entries = 1, pipe = true, flow = true) + entries = 1, flow = true) // No flow control needed out.ready := Mux(out.bits.read, r.ready, b.ready) diff --git a/src/main/scala/uncore/tilelink2/RegisterRouter.scala b/src/main/scala/uncore/tilelink2/RegisterRouter.scala index dddd0a60..89c62021 100644 --- a/src/main/scala/uncore/tilelink2/RegisterRouter.scala +++ b/src/main/scala/uncore/tilelink2/RegisterRouter.scala @@ -44,7 +44,7 @@ class TLRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = // Invoke the register map builder and make it Irrevocable val out = Queue.irrevocable( RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*), - entries = 1, pipe = true, flow = true) + entries = 1, flow = true) // No flow control needed in.valid := a.valid