tilelink2 axi4: RegisterRouter can cut ready dependency
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parent
dc26736f32
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38b6c1c820
@ -49,7 +49,7 @@ class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int
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// Invoke the register map builder and make it Irrevocable
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// Invoke the register map builder and make it Irrevocable
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val out = Queue.irrevocable(
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val out = Queue.irrevocable(
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RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*),
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RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*),
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entries = 1, pipe = true, flow = true)
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entries = 1, flow = true)
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// No flow control needed
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// No flow control needed
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out.ready := Mux(out.bits.read, r.ready, b.ready)
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out.ready := Mux(out.bits.read, r.ready, b.ready)
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@ -44,7 +44,7 @@ class TLRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int =
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// Invoke the register map builder and make it Irrevocable
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// Invoke the register map builder and make it Irrevocable
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val out = Queue.irrevocable(
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val out = Queue.irrevocable(
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RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*),
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RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*),
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entries = 1, pipe = true, flow = true)
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entries = 1, flow = true)
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// No flow control needed
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// No flow control needed
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in.valid := a.valid
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in.valid := a.valid
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