riscv/rocket-chip
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Support non-power-of-2 BTBs; prefer invalid entries

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This commit is contained in:
Andrew Waterman
2013-08-24 17:33:11 -07:00
parent daf23b8f79
commit 3895b75a56
2 changed files with 27 additions and 7 deletions
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16
rocket/src/main/scala/dpath_util.scala
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@ -23,27 +23,29 @@ class rocketDpathBTB(entries: Int) extends Module
{
val io = new DpathBTBIO
val repl_way = LFSR16(io.wen)(log2Up(entries)-1,0) // TODO: pseudo-LRU
var hit_reduction = Bool(false)
val hit = Bool()
val update = Bool()
var update_reduction = Bool(false)
val valid = Vec.fill(entries){Reg(init=Bool(false))}
val hits = Vec.fill(entries){Bool()}
val updates = Vec.fill(entries){Bool()}
val targets = Vec.fill(entries){Reg(UInt())}
val anyUpdate = updates.toBits.orR
val random_way = Random(entries, io.wen)
val invalid_way = valid.indexWhere((x: Bool) => !x)
val repl_way = Mux(valid.contains(Bool(false)), invalid_way, random_way)
for (i <- 0 until entries) {
val tag = Reg(UInt())
val valid = Reg(init=Bool(false))
hits(i) := valid && tag === io.current_pc
updates(i) := valid && tag === io.correct_pc
hits(i) := valid(i) && tag === io.current_pc
updates(i) := valid(i) && tag === io.correct_pc
when (io.wen && (updates(i) || !anyUpdate && UInt(i) === repl_way)) {
valid := Bool(false)
valid(i) := Bool(false)
when (!io.clr) {
valid := Bool(true)
valid(i) := Bool(true)
tag := io.correct_pc
targets(i) := io.correct_target
}