riscv/rocket-chip
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Share PMP mask gen between I$ and D$

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This commit is contained in:
Andrew Waterman 2017-03-20 05:21:50 -07:00
parent 86d84959cf
commit 38808f55d5
2 changed files with 18 additions and 8 deletions
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4
src/main/scala/rocket/CSR.scala
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@ -239,7 +239,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
val reg_tselect = Reg(UInt(width = log2Up(nBreakpoints))) val reg_tselect = Reg(UInt(width = log2Up(nBreakpoints)))
val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP)) val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP))
val reg_pmp = Reg(Vec(nPMPs, new PMP)) val reg_pmp = Reg(Vec(nPMPs, new PMPReg))
val reg_mie = Reg(UInt(width = xLen)) val reg_mie = Reg(UInt(width = xLen))
val reg_mideleg = Reg(UInt(width = xLen)) val reg_mideleg = Reg(UInt(width = xLen))
@ -289,7 +289,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
io.interrupt := all_interrupts.orR && !reg_debug && !io.singleStep || reg_singleStepped io.interrupt := all_interrupts.orR && !reg_debug && !io.singleStep || reg_singleStepped
io.interrupt_cause := interruptCause io.interrupt_cause := interruptCause
io.bp := reg_bp take nBreakpoints io.bp := reg_bp take nBreakpoints
io.pmp := reg_pmp io.pmp := reg_pmp.map(PMP(_))
// debug interrupts are only masked by being in debug mode // debug interrupts are only masked by being in debug mode
when (Bool(usingDebug) && reg_dcsr.debugint && !reg_debug) { when (Bool(usingDebug) && reg_dcsr.debugint && !reg_debug) {

22
src/main/scala/rocket/PMP.scala
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@ -19,18 +19,28 @@ class PMPConfig extends Bundle {
object PMP { object PMP {
def lgAlign = 2 def lgAlign = 2
def apply(reg: PMPReg): PMP = {
val pmp = Wire(new PMP()(reg.p))
pmp := reg
pmp.mask := pmp.computeMask
pmp
}
} }
class PMP(implicit p: Parameters) extends CoreBundle()(p) { class PMPReg(implicit p: Parameters) extends CoreBundle()(p) {
import PMP._
val cfg = new PMPConfig val cfg = new PMPConfig
val addr = UInt(width = paddrBits - lgAlign) val addr = UInt(width = paddrBits - PMP.lgAlign)
def locked = cfg.p(1) def locked = cfg.p(1)
def addrLocked(next: PMP) = locked || next.locked && next.cfg.a(1) def addrLocked(next: PMPReg) = locked || next.locked && next.cfg.a(1)
}
private lazy val mask = Cat((0 until paddrBits - lgAlign).scanLeft(cfg.a(0))((m, i) => m && addr(i)).asUInt, UInt((BigInt(1) << lgAlign) - 1, lgAlign)) class PMP(implicit p: Parameters) extends PMPReg {
val mask = UInt(width = paddrBits)
import PMP._
def computeMask = Cat((0 until paddrBits - lgAlign).scanLeft(cfg.a(0))((m, i) => m && addr(i)).asUInt, UInt((BigInt(1) << lgAlign) - 1, lgAlign))
private lazy val comparand = addr << lgAlign private lazy val comparand = addr << lgAlign
private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = { private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = {