From 38808f55d55e8ef14c155b05c2391843a6372bbf Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Mon, 20 Mar 2017 05:21:50 -0700
Subject: [PATCH] Share PMP mask gen between I$ and D$

---
 src/main/scala/rocket/CSR.scala |  4 ++--
 src/main/scala/rocket/PMP.scala | 22 ++++++++++++++++------
 2 files changed, 18 insertions(+), 8 deletions(-)

diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala
index 689fa958..6514eec3 100644
--- a/src/main/scala/rocket/CSR.scala
+++ b/src/main/scala/rocket/CSR.scala
@@ -239,7 +239,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
 
   val reg_tselect = Reg(UInt(width = log2Up(nBreakpoints)))
   val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP))
-  val reg_pmp = Reg(Vec(nPMPs, new PMP))
+  val reg_pmp = Reg(Vec(nPMPs, new PMPReg))
 
   val reg_mie = Reg(UInt(width = xLen))
   val reg_mideleg = Reg(UInt(width = xLen))
@@ -289,7 +289,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
   io.interrupt := all_interrupts.orR && !reg_debug && !io.singleStep || reg_singleStepped
   io.interrupt_cause := interruptCause
   io.bp := reg_bp take nBreakpoints
-  io.pmp := reg_pmp
+  io.pmp := reg_pmp.map(PMP(_))
 
   // debug interrupts are only masked by being in debug mode
   when (Bool(usingDebug) && reg_dcsr.debugint && !reg_debug) {
diff --git a/src/main/scala/rocket/PMP.scala b/src/main/scala/rocket/PMP.scala
index af7d5518..f633d91c 100644
--- a/src/main/scala/rocket/PMP.scala
+++ b/src/main/scala/rocket/PMP.scala
@@ -19,18 +19,28 @@ class PMPConfig extends Bundle {
 
 object PMP {
   def lgAlign = 2
+
+  def apply(reg: PMPReg): PMP = {
+    val pmp = Wire(new PMP()(reg.p))
+    pmp := reg
+    pmp.mask := pmp.computeMask
+    pmp
+  }
 }
 
-class PMP(implicit p: Parameters) extends CoreBundle()(p) {
-  import PMP._
-
+class PMPReg(implicit p: Parameters) extends CoreBundle()(p) {
   val cfg = new PMPConfig
-  val addr = UInt(width = paddrBits - lgAlign)
+  val addr = UInt(width = paddrBits - PMP.lgAlign)
 
   def locked = cfg.p(1)
-  def addrLocked(next: PMP) = locked || next.locked && next.cfg.a(1)
+  def addrLocked(next: PMPReg) = locked || next.locked && next.cfg.a(1)
+}
 
-  private lazy val mask = Cat((0 until paddrBits - lgAlign).scanLeft(cfg.a(0))((m, i) => m && addr(i)).asUInt, UInt((BigInt(1) << lgAlign) - 1, lgAlign))
+class PMP(implicit p: Parameters) extends PMPReg {
+  val mask = UInt(width = paddrBits)
+
+  import PMP._
+  def computeMask = Cat((0 until paddrBits - lgAlign).scanLeft(cfg.a(0))((m, i) => m && addr(i)).asUInt, UInt((BigInt(1) << lgAlign) - 1, lgAlign))
   private lazy val comparand = addr << lgAlign
 
   private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = {