riscv/rocket-chip
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Share PMP mask gen between I$ and D$

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This commit is contained in:
Andrew Waterman
2017-03-20 05:21:50 -07:00
parent 86d84959cf
commit 38808f55d5
2 changed files with 18 additions and 8 deletions
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4
src/main/scala/rocket/CSR.scala
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@ -239,7 +239,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
val reg_tselect = Reg(UInt(width = log2Up(nBreakpoints)))
val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP))
val reg_pmp = Reg(Vec(nPMPs, new PMP))
val reg_pmp = Reg(Vec(nPMPs, new PMPReg))
val reg_mie = Reg(UInt(width = xLen))
val reg_mideleg = Reg(UInt(width = xLen))
@ -289,7 +289,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
io.interrupt := all_interrupts.orR && !reg_debug && !io.singleStep || reg_singleStepped
io.interrupt_cause := interruptCause
io.bp := reg_bp take nBreakpoints
io.pmp := reg_pmp
io.pmp := reg_pmp.map(PMP(_))
// debug interrupts are only masked by being in debug mode
when (Bool(usingDebug) && reg_dcsr.debugint && !reg_debug) {