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reset -> resetVal, getReset -> reset

This commit is contained in:
Huy Vo 2013-08-12 20:51:54 -07:00
parent 1a9e43aa11
commit 387cf0ebe0
6 changed files with 11 additions and 11 deletions

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@ -42,7 +42,7 @@ class Core(implicit conf: RocketConfiguration) extends Module
} else null } else null
if (conf.vec) { if (conf.vec) {
val vu = Module(new vu(RegUpdate(this.getReset))) val vu = Module(new vu(RegUpdate(this.reset)))
val vdtlb = Module(new TLB(8)) val vdtlb = Module(new TLB(8))
ptw += vdtlb.io.ptw ptw += vdtlb.io.ptw

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@ -407,7 +407,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
val wb_reg_div_mul_val = RegReset(Bool(false)) val wb_reg_div_mul_val = RegReset(Bool(false))
val take_pc = Bool() val take_pc = Bool()
val pc_taken = Reg(update = take_pc, reset = Bool(false)) val pc_taken = Reg(update = take_pc, resetVal = Bool(false))
val take_pc_wb = Bool() val take_pc_wb = Bool()
val ctrl_killd = Bool() val ctrl_killd = Bool()
val ctrl_killx = Bool() val ctrl_killx = Bool()

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@ -278,7 +278,7 @@ class PCR(implicit conf: RocketConfiguration) extends Module
io.host.ipi_rep.ready := Bool(true) io.host.ipi_rep.ready := Bool(true)
when (io.host.ipi_rep.valid) { r_irq_ipi := Bool(true) } when (io.host.ipi_rep.valid) { r_irq_ipi := Bool(true) }
when(this.getReset) { when(this.reset) {
reg_status.et := false reg_status.et := false
reg_status.ef := false reg_status.ef := false
reg_status.ev := false reg_status.ev := false

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@ -465,10 +465,10 @@ class FPU(sfma_latency: Int, dfma_latency: Int) extends Module
when (io.ctrl.valid) { when (io.ctrl.valid) {
ex_reg_inst := io.dpath.inst ex_reg_inst := io.dpath.inst
} }
val ex_reg_valid = Reg(update=io.ctrl.valid, reset=Bool(false)) val ex_reg_valid = Reg(update=io.ctrl.valid, resetVal=Bool(false))
val mem_reg_valid = Reg(update=ex_reg_valid && !io.ctrl.killx, reset=Bool(false)) val mem_reg_valid = Reg(update=ex_reg_valid && !io.ctrl.killx, resetVal=Bool(false))
val killm = io.ctrl.killm || io.ctrl.nack_mem val killm = io.ctrl.killm || io.ctrl.nack_mem
val wb_reg_valid = Reg(update=mem_reg_valid && !killm, reset=Bool(false)) val wb_reg_valid = Reg(update=mem_reg_valid && !killm, resetVal=Bool(false))
val fp_decoder = Module(new FPUDecoder) val fp_decoder = Module(new FPUDecoder)
fp_decoder.io.inst := io.dpath.inst fp_decoder.io.inst := io.dpath.inst

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@ -756,15 +756,15 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
val mshrs = Module(new MSHRFile) val mshrs = Module(new MSHRFile)
io.cpu.req.ready := Bool(true) io.cpu.req.ready := Bool(true)
val s1_valid = Reg(update=io.cpu.req.fire(), reset=Bool(false)) val s1_valid = Reg(update=io.cpu.req.fire(), resetVal=Bool(false))
val s1_req = Reg(io.cpu.req.bits.clone) val s1_req = Reg(io.cpu.req.bits.clone)
val s1_valid_masked = s1_valid && !io.cpu.req.bits.kill val s1_valid_masked = s1_valid && !io.cpu.req.bits.kill
val s1_replay = RegReset(Bool(false)) val s1_replay = RegReset(Bool(false))
val s1_clk_en = Reg(Bool()) val s1_clk_en = Reg(Bool())
val s2_valid = Reg(update=s1_valid_masked, reset=Bool(false)) val s2_valid = Reg(update=s1_valid_masked, resetVal=Bool(false))
val s2_req = Reg(io.cpu.req.bits.clone) val s2_req = Reg(io.cpu.req.bits.clone)
val s2_replay = Reg(update=s1_replay, reset=Bool(false)) val s2_replay = Reg(update=s1_replay, resetVal=Bool(false))
val s2_recycle = Bool() val s2_recycle = Bool()
val s2_valid_masked = Bool() val s2_valid_masked = Bool()
@ -993,7 +993,7 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends
FIFOedLogicalNetworkIOWrapper(wb.io.release_data) <> io.mem.release.data FIFOedLogicalNetworkIOWrapper(wb.io.release_data) <> io.mem.release.data
// store->load bypassing // store->load bypassing
val s4_valid = Reg(update=s3_valid, reset=Bool(false)) val s4_valid = Reg(update=s3_valid, resetVal=Bool(false))
val s4_req = RegEn(s3_req, s3_valid && metaReadArb.io.out.valid) val s4_req = RegEn(s3_req, s3_valid && metaReadArb.io.out.valid)
val bypasses = List( val bypasses = List(
((s2_valid_masked || s2_replay) && !s2_sc_fail, s2_req, amoalu.io.out), ((s2_valid_masked || s2_replay) && !s2_sc_fail, s2_req, amoalu.io.out),

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@ -19,7 +19,7 @@ case class RocketConfiguration(tl: TileLinkConfiguration,
if (fastLoadByte) require(fastLoadWord) if (fastLoadByte) require(fastLoadWord)
} }
class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module(reset = resetSignal) with ClientCoherenceAgent class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = resetSignal) with ClientCoherenceAgent
{ {
val memPorts = 2 + confIn.vec val memPorts = 2 + confIn.vec
val dcachePortId = 0 val dcachePortId = 0