riscv/rocket-chip
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tilelink2: bring IntNode parameters up to the current standard

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This commit is contained in:
Wesley W. Terpstra 2017-03-01 18:23:28 -08:00
parent 5bd9f18e5b
commit 38489ad9b0
7 changed files with 23 additions and 16 deletions
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2
src/main/scala/coreplex/RocketTiles.scala
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@ -23,7 +23,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
private val crossing = p(RocketCrossing) private val crossing = p(RocketCrossing)
private val configs = p(RocketTilesKey) private val configs = p(RocketTilesKey)
private val rocketTileIntNodes = configs.map { _ => IntInternalOutputNode() } private val rocketTileIntNodes = configs.map { _ => IntInternalOutputNode(IntSinkPortSimple()) }
rocketTileIntNodes.foreach { _ := plic.intnode } rocketTileIntNodes.foreach { _ := plic.intnode }
private def wireInterrupts(x: TileInterrupts, i: Int) { private def wireInterrupts(x: TileInterrupts, i: Int) {

2
src/main/scala/rocketchip/Periphery.scala
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@ -58,7 +58,7 @@ trait PeripheryExtInterrupts {
} }
val nExtInterrupts = p(NExtTopInterrupts) val nExtInterrupts = p(NExtTopInterrupts)
val extInterrupts = IntInternalInputNode(nExtInterrupts, device.int) val extInterrupts = IntInternalInputNode(IntSourcePortSimple(num = nExtInterrupts, resources = device.int))
val extInterruptXing = LazyModule(new IntXing) val extInterruptXing = LazyModule(new IntXing)
intBus.intnode := extInterruptXing.intnode intBus.intnode := extInterruptXing.intnode

2
src/main/scala/uncore/ahb/RegisterRouter.scala
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@ -77,7 +77,7 @@ object AHBRegisterNode
abstract class AHBRegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule abstract class AHBRegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule
{ {
val node = AHBRegisterNode(address, concurrency, beatBytes, undefZero, executable) val node = AHBRegisterNode(address, concurrency, beatBytes, undefZero, executable)
val intnode = uncore.tilelink2.IntSourceNode(interrupts) val intnode = uncore.tilelink2.IntSourceNode(uncore.tilelink2.IntSourcePortSimple(num = interrupts))
} }
case class AHBRegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[AHBBundle])(implicit val p: Parameters) case class AHBRegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[AHBBundle])(implicit val p: Parameters)

2
src/main/scala/uncore/apb/RegisterRouter.scala
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@ -61,7 +61,7 @@ object APBRegisterNode
abstract class APBRegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule abstract class APBRegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule
{ {
val node = APBRegisterNode(address, concurrency, beatBytes, undefZero, executable) val node = APBRegisterNode(address, concurrency, beatBytes, undefZero, executable)
val intnode = uncore.tilelink2.IntSourceNode(interrupts) val intnode = uncore.tilelink2.IntSourceNode(uncore.tilelink2.IntSourcePortSimple(num = interrupts))
} }
case class APBRegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[APBBundle])(implicit val p: Parameters) case class APBRegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[APBBundle])(implicit val p: Parameters)

2
src/main/scala/uncore/axi4/RegisterRouter.scala
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@ -82,7 +82,7 @@ object AXI4RegisterNode
abstract class AXI4RegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule abstract class AXI4RegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule
{ {
val node = AXI4RegisterNode(address, concurrency, beatBytes, undefZero, executable) val node = AXI4RegisterNode(address, concurrency, beatBytes, undefZero, executable)
val intnode = uncore.tilelink2.IntSourceNode(interrupts) val intnode = uncore.tilelink2.IntSourceNode(uncore.tilelink2.IntSourcePortSimple(num = interrupts))
} }
case class AXI4RegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[AXI4Bundle])(implicit val p: Parameters) case class AXI4RegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[AXI4Bundle])(implicit val p: Parameters)

27
src/main/scala/uncore/tilelink2/IntNodes.scala
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@ -46,8 +46,19 @@ case class IntSourcePortParameters(sources: Seq[IntSourceParameters])
// The interrupts must perfectly cover the range // The interrupts must perfectly cover the range
require (sources.isEmpty || sources.map(_.range.end).max == num) require (sources.isEmpty || sources.map(_.range.end).max == num)
} }
object IntSourcePortSimple
{
def apply(num: Int = 1, ports: Int = 1, sources: Int = 1, resources: Seq[Resource] = Nil) =
if (num == 0) Nil else
Seq.fill(ports)(IntSourcePortParameters(Seq.fill(sources)(IntSourceParameters(range = IntRange(0, num), resources = resources))))
}
case class IntSinkPortParameters(sinks: Seq[IntSinkParameters]) case class IntSinkPortParameters(sinks: Seq[IntSinkParameters])
object IntSinkPortSimple
{
def apply(ports: Int = 1, sinks: Int = 1) =
Seq.fill(ports)(IntSinkPortParameters(Seq.fill(sinks)(IntSinkParameters())))
}
case class IntEdge(source: IntSourcePortParameters, sink: IntSinkPortParameters) case class IntEdge(source: IntSourcePortParameters, sink: IntSinkPortParameters)
@ -76,10 +87,8 @@ object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, In
} }
case class IntIdentityNode() extends IdentityNode(IntImp) case class IntIdentityNode() extends IdentityNode(IntImp)
case class IntSourceNode(num: Int, resources: Seq[Resource] = Nil) extends SourceNode(IntImp)( case class IntSourceNode(portParams: Seq[IntSourcePortParameters]) extends SourceNode(IntImp)(portParams)
if (num == 0) Seq() else Seq(IntSourcePortParameters(Seq(IntSourceParameters(num, resources))))) case class IntSinkNode(portParams: Seq[IntSinkPortParameters]) extends SinkNode(IntImp)(portParams)
case class IntSinkNode() extends SinkNode(IntImp)(
Seq(IntSinkPortParameters(Seq(IntSinkParameters()))))
case class IntNexusNode( case class IntNexusNode(
sourceFn: Seq[IntSourcePortParameters] => IntSourcePortParameters, sourceFn: Seq[IntSourcePortParameters] => IntSourcePortParameters,
@ -91,13 +100,11 @@ case class IntNexusNode(
case class IntOutputNode() extends OutputNode(IntImp) case class IntOutputNode() extends OutputNode(IntImp)
case class IntInputNode() extends InputNode(IntImp) case class IntInputNode() extends InputNode(IntImp)
case class IntBlindOutputNode() extends BlindOutputNode(IntImp)(Seq(IntSinkPortParameters(Seq(IntSinkParameters())))) case class IntBlindOutputNode(portParams: Seq[IntSinkPortParameters]) extends BlindOutputNode(IntImp)(portParams)
case class IntBlindInputNode(num: Int, resources: Seq[Resource] = Nil) extends BlindInputNode(IntImp)( case class IntBlindInputNode(portParams: Seq[IntSourcePortParameters]) extends BlindInputNode(IntImp)(portParams)
Seq(IntSourcePortParameters(Seq(IntSourceParameters(num, resources)))))
case class IntInternalOutputNode() extends InternalOutputNode(IntImp)(Seq(IntSinkPortParameters(Seq(IntSinkParameters())))) case class IntInternalOutputNode(portParams: Seq[IntSinkPortParameters]) extends InternalOutputNode(IntImp)(portParams)
case class IntInternalInputNode(num: Int, resources: Seq[Resource] = Nil) extends InternalInputNode(IntImp)( case class IntInternalInputNode(portParams: Seq[IntSourcePortParameters]) extends InternalInputNode(IntImp)(portParams)
Seq(IntSourcePortParameters(Seq(IntSourceParameters(num, resources)))))
class IntXbar()(implicit p: Parameters) extends LazyModule class IntXbar()(implicit p: Parameters) extends LazyModule
{ {

2
src/main/scala/uncore/tilelink2/RegisterRouter.scala
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@ -99,7 +99,7 @@ abstract class TLRegisterRouterBase(devname: String, devcompat: Seq[String], val
{ {
val device = new SimpleDevice(devname, devcompat) val device = new SimpleDevice(devname, devcompat)
val node = TLRegisterNode(address, device, "reg", concurrency, beatBytes, undefZero, executable) val node = TLRegisterNode(address, device, "reg", concurrency, beatBytes, undefZero, executable)
val intnode = IntSourceNode(interrupts, Seq(Resource(device, "int"))) val intnode = IntSourceNode(IntSourcePortSimple(num = interrupts, resources = Seq(Resource(device, "int"))))
} }
case class TLRegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[TLBundle])(implicit val p: Parameters) case class TLRegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[TLBundle])(implicit val p: Parameters)