From 38489ad9b0ed8d4dc404921ce90e52115fb740d6 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 1 Mar 2017 18:23:28 -0800 Subject: [PATCH] tilelink2: bring IntNode parameters up to the current standard --- src/main/scala/coreplex/RocketTiles.scala | 2 +- src/main/scala/rocketchip/Periphery.scala | 2 +- .../scala/uncore/ahb/RegisterRouter.scala | 2 +- .../scala/uncore/apb/RegisterRouter.scala | 2 +- .../scala/uncore/axi4/RegisterRouter.scala | 2 +- .../scala/uncore/tilelink2/IntNodes.scala | 27 ++++++++++++------- .../uncore/tilelink2/RegisterRouter.scala | 2 +- 7 files changed, 23 insertions(+), 16 deletions(-) diff --git a/src/main/scala/coreplex/RocketTiles.scala b/src/main/scala/coreplex/RocketTiles.scala index 5beed003..3202f128 100644 --- a/src/main/scala/coreplex/RocketTiles.scala +++ b/src/main/scala/coreplex/RocketTiles.scala @@ -23,7 +23,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform { private val crossing = p(RocketCrossing) private val configs = p(RocketTilesKey) - private val rocketTileIntNodes = configs.map { _ => IntInternalOutputNode() } + private val rocketTileIntNodes = configs.map { _ => IntInternalOutputNode(IntSinkPortSimple()) } rocketTileIntNodes.foreach { _ := plic.intnode } private def wireInterrupts(x: TileInterrupts, i: Int) { diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala index b72ae9e3..ce91fbdb 100644 --- a/src/main/scala/rocketchip/Periphery.scala +++ b/src/main/scala/rocketchip/Periphery.scala @@ -58,7 +58,7 @@ trait PeripheryExtInterrupts { } val nExtInterrupts = p(NExtTopInterrupts) - val extInterrupts = IntInternalInputNode(nExtInterrupts, device.int) + val extInterrupts = IntInternalInputNode(IntSourcePortSimple(num = nExtInterrupts, resources = device.int)) val extInterruptXing = LazyModule(new IntXing) intBus.intnode := extInterruptXing.intnode diff --git a/src/main/scala/uncore/ahb/RegisterRouter.scala b/src/main/scala/uncore/ahb/RegisterRouter.scala index e514292e..2621e41f 100644 --- a/src/main/scala/uncore/ahb/RegisterRouter.scala +++ b/src/main/scala/uncore/ahb/RegisterRouter.scala @@ -77,7 +77,7 @@ object AHBRegisterNode abstract class AHBRegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule { val node = AHBRegisterNode(address, concurrency, beatBytes, undefZero, executable) - val intnode = uncore.tilelink2.IntSourceNode(interrupts) + val intnode = uncore.tilelink2.IntSourceNode(uncore.tilelink2.IntSourcePortSimple(num = interrupts)) } case class AHBRegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[AHBBundle])(implicit val p: Parameters) diff --git a/src/main/scala/uncore/apb/RegisterRouter.scala b/src/main/scala/uncore/apb/RegisterRouter.scala index 62585d0e..b8e3a9ae 100644 --- a/src/main/scala/uncore/apb/RegisterRouter.scala +++ b/src/main/scala/uncore/apb/RegisterRouter.scala @@ -61,7 +61,7 @@ object APBRegisterNode abstract class APBRegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule { val node = APBRegisterNode(address, concurrency, beatBytes, undefZero, executable) - val intnode = uncore.tilelink2.IntSourceNode(interrupts) + val intnode = uncore.tilelink2.IntSourceNode(uncore.tilelink2.IntSourcePortSimple(num = interrupts)) } case class APBRegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[APBBundle])(implicit val p: Parameters) diff --git a/src/main/scala/uncore/axi4/RegisterRouter.scala b/src/main/scala/uncore/axi4/RegisterRouter.scala index 2da706bf..b7d51611 100644 --- a/src/main/scala/uncore/axi4/RegisterRouter.scala +++ b/src/main/scala/uncore/axi4/RegisterRouter.scala @@ -82,7 +82,7 @@ object AXI4RegisterNode abstract class AXI4RegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule { val node = AXI4RegisterNode(address, concurrency, beatBytes, undefZero, executable) - val intnode = uncore.tilelink2.IntSourceNode(interrupts) + val intnode = uncore.tilelink2.IntSourceNode(uncore.tilelink2.IntSourcePortSimple(num = interrupts)) } case class AXI4RegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[AXI4Bundle])(implicit val p: Parameters) diff --git a/src/main/scala/uncore/tilelink2/IntNodes.scala b/src/main/scala/uncore/tilelink2/IntNodes.scala index 110d89ef..eb241918 100644 --- a/src/main/scala/uncore/tilelink2/IntNodes.scala +++ b/src/main/scala/uncore/tilelink2/IntNodes.scala @@ -46,8 +46,19 @@ case class IntSourcePortParameters(sources: Seq[IntSourceParameters]) // The interrupts must perfectly cover the range require (sources.isEmpty || sources.map(_.range.end).max == num) } +object IntSourcePortSimple +{ + def apply(num: Int = 1, ports: Int = 1, sources: Int = 1, resources: Seq[Resource] = Nil) = + if (num == 0) Nil else + Seq.fill(ports)(IntSourcePortParameters(Seq.fill(sources)(IntSourceParameters(range = IntRange(0, num), resources = resources)))) +} case class IntSinkPortParameters(sinks: Seq[IntSinkParameters]) +object IntSinkPortSimple +{ + def apply(ports: Int = 1, sinks: Int = 1) = + Seq.fill(ports)(IntSinkPortParameters(Seq.fill(sinks)(IntSinkParameters()))) +} case class IntEdge(source: IntSourcePortParameters, sink: IntSinkPortParameters) @@ -76,10 +87,8 @@ object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, In } case class IntIdentityNode() extends IdentityNode(IntImp) -case class IntSourceNode(num: Int, resources: Seq[Resource] = Nil) extends SourceNode(IntImp)( - if (num == 0) Seq() else Seq(IntSourcePortParameters(Seq(IntSourceParameters(num, resources))))) -case class IntSinkNode() extends SinkNode(IntImp)( - Seq(IntSinkPortParameters(Seq(IntSinkParameters())))) +case class IntSourceNode(portParams: Seq[IntSourcePortParameters]) extends SourceNode(IntImp)(portParams) +case class IntSinkNode(portParams: Seq[IntSinkPortParameters]) extends SinkNode(IntImp)(portParams) case class IntNexusNode( sourceFn: Seq[IntSourcePortParameters] => IntSourcePortParameters, @@ -91,13 +100,11 @@ case class IntNexusNode( case class IntOutputNode() extends OutputNode(IntImp) case class IntInputNode() extends InputNode(IntImp) -case class IntBlindOutputNode() extends BlindOutputNode(IntImp)(Seq(IntSinkPortParameters(Seq(IntSinkParameters())))) -case class IntBlindInputNode(num: Int, resources: Seq[Resource] = Nil) extends BlindInputNode(IntImp)( - Seq(IntSourcePortParameters(Seq(IntSourceParameters(num, resources))))) +case class IntBlindOutputNode(portParams: Seq[IntSinkPortParameters]) extends BlindOutputNode(IntImp)(portParams) +case class IntBlindInputNode(portParams: Seq[IntSourcePortParameters]) extends BlindInputNode(IntImp)(portParams) -case class IntInternalOutputNode() extends InternalOutputNode(IntImp)(Seq(IntSinkPortParameters(Seq(IntSinkParameters())))) -case class IntInternalInputNode(num: Int, resources: Seq[Resource] = Nil) extends InternalInputNode(IntImp)( - Seq(IntSourcePortParameters(Seq(IntSourceParameters(num, resources))))) +case class IntInternalOutputNode(portParams: Seq[IntSinkPortParameters]) extends InternalOutputNode(IntImp)(portParams) +case class IntInternalInputNode(portParams: Seq[IntSourcePortParameters]) extends InternalInputNode(IntImp)(portParams) class IntXbar()(implicit p: Parameters) extends LazyModule { diff --git a/src/main/scala/uncore/tilelink2/RegisterRouter.scala b/src/main/scala/uncore/tilelink2/RegisterRouter.scala index 28ea03ac..e46c2a56 100644 --- a/src/main/scala/uncore/tilelink2/RegisterRouter.scala +++ b/src/main/scala/uncore/tilelink2/RegisterRouter.scala @@ -99,7 +99,7 @@ abstract class TLRegisterRouterBase(devname: String, devcompat: Seq[String], val { val device = new SimpleDevice(devname, devcompat) val node = TLRegisterNode(address, device, "reg", concurrency, beatBytes, undefZero, executable) - val intnode = IntSourceNode(interrupts, Seq(Resource(device, "int"))) + val intnode = IntSourceNode(IntSourcePortSimple(num = interrupts, resources = Seq(Resource(device, "int")))) } case class TLRegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[TLBundle])(implicit val p: Parameters)