riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tilelink2: bring IntNode parameters up to the current standard

Browse Source
This commit is contained in:
Wesley W. Terpstra
2017-03-01 18:23:28 -08:00
parent 5bd9f18e5b
commit 38489ad9b0
7 changed files with 23 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/uncore/axi4/RegisterRouter.scala
View File

@ -82,7 +82,7 @@ object AXI4RegisterNode
abstract class AXI4RegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule
{
val node = AXI4RegisterNode(address, concurrency, beatBytes, undefZero, executable)
val intnode = uncore.tilelink2.IntSourceNode(interrupts)
val intnode = uncore.tilelink2.IntSourceNode(uncore.tilelink2.IntSourcePortSimple(num = interrupts))
}
case class AXI4RegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[AXI4Bundle])(implicit val p: Parameters)