riscv/rocket-chip
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tilelink2: bring IntNode parameters up to the current standard

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Wesley W. Terpstra committed 2017-03-02 21:19:22 -08:00
1 parent 5bd9f18e5b
commit 38489ad9b0
7 files changed
+23 -16
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src/main/scala/uncore/ahb/RegisterRouter.scala
+1 -1
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@@ -77,7 +77,7 @@ object AHBRegisterNode
abstract class AHBRegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule
{
val node = AHBRegisterNode(address, concurrency, beatBytes, undefZero, executable)
val intnode = uncore.tilelink2.IntSourceNode(interrupts)
val intnode = uncore.tilelink2.IntSourceNode(uncore.tilelink2.IntSourcePortSimple(num = interrupts))
}
case class AHBRegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[AHBBundle])(implicit val p: Parameters)