riscv/rocket-chip
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tilelink2: bring IntNode parameters up to the current standard

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This commit is contained in:
Wesley W. Terpstra
2017-03-01 18:23:28 -08:00
parent 5bd9f18e5b
commit 38489ad9b0
7 changed files with 23 additions and 16 deletions
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2
src/main/scala/rocketchip/Periphery.scala
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@ -58,7 +58,7 @@ trait PeripheryExtInterrupts {
}
val nExtInterrupts = p(NExtTopInterrupts)
val extInterrupts = IntInternalInputNode(nExtInterrupts, device.int)
val extInterrupts = IntInternalInputNode(IntSourcePortSimple(num = nExtInterrupts, resources = device.int))
val extInterruptXing = LazyModule(new IntXing)
intBus.intnode := extInterruptXing.intnode