riscv/rocket-chip
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tilelink2: bring IntNode parameters up to the current standard

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Wesley W. Terpstra committed 2017-03-02 21:19:22 -08:00
1 parent 5bd9f18e5b
commit 38489ad9b0
7 files changed
+23 -16
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src/main/scala/rocketchip/Periphery.scala
+1 -1
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@@ -58,7 +58,7 @@ trait PeripheryExtInterrupts {
}
val nExtInterrupts = p(NExtTopInterrupts)
val extInterrupts = IntInternalInputNode(nExtInterrupts, device.int)
val extInterrupts = IntInternalInputNode(IntSourcePortSimple(num = nExtInterrupts, resources = device.int))
val extInterruptXing = LazyModule(new IntXing)
intBus.intnode := extInterruptXing.intnode