riscv/rocket-chip
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tilelink2: bring IntNode parameters up to the current standard

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Wesley W. Terpstra
2017-03-01 18:23:28 -08:00
parent 5bd9f18e5b
commit 38489ad9b0
7 changed files with 23 additions and 16 deletions
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2
src/main/scala/coreplex/RocketTiles.scala
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@ -23,7 +23,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
private val crossing = p(RocketCrossing)
private val configs = p(RocketTilesKey)
private val rocketTileIntNodes = configs.map { _ => IntInternalOutputNode() }
private val rocketTileIntNodes = configs.map { _ => IntInternalOutputNode(IntSinkPortSimple()) }
rocketTileIntNodes.foreach { _ := plic.intnode }
private def wireInterrupts(x: TileInterrupts, i: Int) {