riscv/rocket-chip
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pipeline reset to the vector unit

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This commit is contained in:
Andrew Waterman 2013-01-28 17:56:32 -08:00
parent f2df6147df
commit 37c67f1d87
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/core.scala
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@ -43,7 +43,7 @@ class Core(implicit conf: RocketConfiguration) extends Component
} else null } else null
if (conf.vec) { if (conf.vec) {
val vu = new vu() val vu = new vu(Reg(reset))
val vdtlb = new TLB(8) val vdtlb = new TLB(8)
ptw += vdtlb.io.ptw ptw += vdtlb.io.ptw