rocketchip: move from using cde to config

src/main/scala/uncore/Builder.scala

@@ -1,7 +1,7 @@
 package uncore
 
 import Chisel._
-import cde.{Config, Parameters, ParameterDump, Knob, Dump, CDEMatchError}
+import config._
 import junctions.PAddrBits
 import uncore.tilelink._
 import uncore.agents._

src/main/scala/uncore/agents/Agents.scala

@@ -3,7 +3,7 @@
 package uncore.agents
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import junctions.PAddrBits
 import uncore.tilelink._
 import uncore.converters._

src/main/scala/uncore/agents/Broadcast.scala

@@ -8,7 +8,7 @@ import uncore.tilelink._
 import uncore.constants._
 import uncore.util._
 import util._
-import cde.Parameters
+import config._
 
 class L2BroadcastHub(implicit p: Parameters) extends HierarchicalCoherenceAgent()(p) {
 

src/main/scala/uncore/agents/Bufferless.scala

@@ -6,7 +6,7 @@ import Chisel._
 import uncore.coherence._
 import uncore.tilelink._
 import uncore.constants._
-import cde.Parameters
+import config._
 
 
 class BufferlessBroadcastHub(implicit p: Parameters) extends HierarchicalCoherenceAgent()(p) {

src/main/scala/uncore/agents/Cache.scala

@@ -12,7 +12,7 @@ import uncore.tilelink._
 import uncore.constants._
 import uncore.util._
 import util._
-import cde.{Parameters, Field}
+import config._
 
 case class CacheConfig(
   nSets:         Int,

src/main/scala/uncore/agents/Mmio.scala

@@ -2,7 +2,7 @@ package uncore.agents
 
 import Chisel._
 import uncore.tilelink._
-import cde.Parameters
+import config._
 
 class MMIOTileLinkManagerData(implicit p: Parameters)
     extends TLBundle()(p)

src/main/scala/uncore/agents/StatelessBridge.scala

@@ -7,7 +7,7 @@ import uncore.coherence._
 import uncore.tilelink._
 import uncore.constants._
 import uncore.devices._
-import cde.{Parameters, Field, Config}
+import config._
 
 /** The ManagerToClientStateless Bridge does not maintain any state for the messages
   *  which pass through it. It simply passes the messages back and forth without any

src/main/scala/uncore/agents/StoreDataQueue.scala

@@ -3,7 +3,7 @@
 package uncore.agents
 import Chisel._
 import uncore.tilelink._
-import cde.{Parameters, Field}
+import config._
 
 case object L2StoreDataQueueDepth extends Field[Int]
 

src/main/scala/uncore/agents/Trackers.scala

@@ -7,7 +7,7 @@ import uncore.coherence._
 import uncore.tilelink._
 import uncore.util._
 import util._
-import cde.{Field, Parameters}
+import config._
 import scala.math.max
 
 case object EnableL2Logging extends Field[Boolean]

src/main/scala/uncore/coherence/Metadata.scala

@@ -5,7 +5,7 @@ package uncore.coherence
 import Chisel._
 import uncore.tilelink._
 import uncore.constants._
-import cde.{Parameters, Field}
+import config._
 
 /** Identifies the TLId of the inner network in a hierarchical cache controller */ 
 case object InnerTLId extends Field[String]

src/main/scala/uncore/converters/Ahb.scala

@@ -5,7 +5,7 @@ import junctions._
 import uncore.tilelink._
 import uncore.util._
 import uncore.constants._
-import cde.{Parameters, Field}
+import config._
 import HastiConstants._
 
 /* We need to translate TileLink requests into operations we can actually execute on AHB.

src/main/scala/uncore/converters/Nasti.scala

@@ -6,7 +6,7 @@ import util.{ReorderQueue, DecoupledHelper}
 import junctions.NastiConstants._
 import uncore.tilelink._
 import uncore.constants._
-import cde.Parameters
+import config._
 import scala.math.min
 
 class IdMapper(val inIdBits: Int, val outIdBits: Int,

src/main/scala/uncore/converters/Tilelink.scala

@@ -8,7 +8,7 @@ import uncore.util._
 import uncore.constants._
 import uncore.devices.TileLinkTestRAM
 import unittest.UnitTest
-import cde.Parameters
+import config._
 
 /** Utilities for safely wrapping a *UncachedTileLink by pinning probe.ready and release.valid low */
 object TileLinkIOWrapper {

src/main/scala/uncore/devices/Bram.scala

@@ -1,7 +1,7 @@
 package uncore.devices
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import unittest.UnitTest
 import junctions._
 import uncore.tilelink._

src/main/scala/uncore/devices/Debug.scala

@@ -7,7 +7,7 @@ import junctions._
 import util._
 import regmapper._
 import uncore.tilelink2._
-import cde.{Parameters, Config, Field}
+import config._
 
 // *****************************************
 // Constants which are interesting even

src/main/scala/uncore/devices/Plic.scala

@@ -9,7 +9,7 @@ import junctions._
 import diplomacy._
 import regmapper._
 import uncore.tilelink2._
-import cde.Parameters
+import config._
 import scala.math.min
 
 class GatewayPLICIO extends Bundle {

src/main/scala/uncore/devices/Prci.scala

@@ -11,7 +11,7 @@ import uncore.tilelink2._
 import uncore.util._
 import util._
 import scala.math.{min,max}
-import cde.{Parameters, Field}
+import config._
 
 /** Number of tiles */
 case object NTiles extends Field[Int]

src/main/scala/uncore/devices/Rom.scala

@@ -7,7 +7,7 @@ import diplomacy._
 import uncore.tilelink._
 import uncore.tilelink2._
 import uncore.util._
-import cde.{Parameters, Field}
+import config._
 
 class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4) extends LazyModule
 {

src/main/scala/uncore/tilelink/Arbiters.scala

@@ -1,7 +1,7 @@
 package uncore.tilelink
 import Chisel._
 import junctions._
-import cde.{Parameters, Field}
+import config._
 
 /** Utility functions for constructing TileLinkIO arbiters */
 trait TileLinkArbiterLike extends HasTileLinkParameters {

src/main/scala/uncore/tilelink/Definitions.scala

@@ -7,7 +7,7 @@ import uncore.coherence.CoherencePolicy
 import uncore.constants._
 import util._
 import scala.math.max
-import cde.{Parameters, Field}
+import config._
 
 case object CacheBlockOffsetBits extends Field[Int]
 case object AmoAluOperandBits extends Field[Int]

src/main/scala/uncore/tilelink/Drivers.scala

@@ -5,7 +5,7 @@ import junctions._
 import uncore.constants._
 import uncore.util._
 import util._
-import cde.Parameters
+import config._
 
 abstract class Driver(implicit p: Parameters) extends TLModule()(p) {
   val io = new Bundle {

src/main/scala/uncore/tilelink/Interconnect.scala

@@ -4,7 +4,7 @@ import Chisel._
 import junctions._
 import scala.collection.mutable.ArraySeq
 import uncore.util._
-import cde.{Parameters, Field}
+import config._
 
 
 /** PortedTileLinkNetworks combine a TileLink protocol with a particular physical

src/main/scala/uncore/tilelink/Network.scala

@@ -4,7 +4,7 @@ package uncore.tilelink
 
 import Chisel._
 import uncore.util._
-import cde.{Parameters, Field}
+import config._
 
 case object LNEndpoints extends Field[Int]
 case object LNHeaderBits extends Field[Int]

src/main/scala/uncore/tilelink2/Legacy.scala

@@ -4,7 +4,7 @@ package uncore.tilelink2
 
 import Chisel._
 import diplomacy._
-import cde.Parameters
+import config._
 import uncore.tilelink._
 import uncore.constants._
 

src/main/scala/uncore/util/AmoAlu.scala

@@ -4,7 +4,7 @@ package uncore.util
 
 import Chisel._
 import uncore.tilelink._
-import cde.Parameters
+import config._
 import uncore.constants._
 
 class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) {

src/main/scala/uncore/util/Counters.scala

@@ -3,7 +3,7 @@ package uncore.util
 import Chisel._
 import uncore.tilelink._
 import util.TwoWayCounter
-import cde.Parameters
+import config._
 
 class BeatCounterStatus extends Bundle {
   val idx = UInt()

src/main/scala/uncore/util/Enqueuer.scala

@@ -2,7 +2,7 @@ package uncore.util
 
 import Chisel._
 import uncore.tilelink._
-import cde.Parameters
+import config._
 
 /** Struct for describing per-channel queue depths */
 case class TileLinkDepths(acq: Int, prb: Int, rel: Int, gnt: Int, fin: Int)