rocketchip: move from using cde to config

src/main/scala/rocket/arbiter.scala

@@ -3,7 +3,7 @@
 package rocket
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import util.{ParameterizedBundle, DecoupledHelper}
 
 class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module

src/main/scala/rocket/breakpoint.scala

@@ -5,7 +5,7 @@ package rocket
 import Chisel._
 import util._
 import Chisel.ImplicitConversions._
-import cde.Parameters
+import config._
 
 class BPControl(implicit p: Parameters) extends CoreBundle()(p) {
   val ttype = UInt(width = 4)

src/main/scala/rocket/btb.scala

@@ -3,7 +3,7 @@
 package rocket
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import util._
 import Chisel.ImplicitConversions._
 import uncore.agents.PseudoLRU

src/main/scala/rocket/csr.scala

@@ -4,7 +4,7 @@ package rocket
 
 import Chisel._
 import Instructions._
-import cde.{Parameters, Field}
+import config._
 import uncore.devices._
 import util._
 import Chisel.ImplicitConversions._

src/main/scala/rocket/dcache.scala

@@ -12,7 +12,7 @@ import uncore.util._
 import util._
 import TLMessages._
 import Chisel.ImplicitConversions._
-import cde.{Parameters, Field}
+import config._
 
 class DCacheDataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
   val addr = Bits(width = untagBits)

src/main/scala/rocket/dpath_alu.scala

@@ -3,7 +3,7 @@
 package rocket
 
 import Chisel._
-import cde.{Parameters, Field}
+import config._
 import Instructions._
 
 object ALU

src/main/scala/rocket/fpu.scala

@@ -8,7 +8,7 @@ import util._
 import Chisel.ImplicitConversions._
 import FPConstants._
 import uncore.constants.MemoryOpConstants._
-import cde.{Parameters, Field}
+import config._
 
 case class FPUConfig(
   divSqrt: Boolean = true,

src/main/scala/rocket/frontend.scala

@@ -4,7 +4,7 @@ import Chisel._
 import uncore.tilelink._
 import util._
 import Chisel.ImplicitConversions._
-import cde.{Parameters, Field}
+import config._
 
 class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) {
   val pc = UInt(width = vaddrBitsExtended)

src/main/scala/rocket/ibuf.scala

@@ -5,7 +5,7 @@ package rocket
 import Chisel._
 import util._
 import Chisel.ImplicitConversions._
-import cde.{Parameters, Field}
+import config._
 
 class Instruction(implicit val p: Parameters) extends ParameterizedBundle with HasCoreParameters {
   val pf0 = Bool() // page fault on first half of instruction

src/main/scala/rocket/icache.scala

@@ -6,7 +6,7 @@ import uncore.tilelink._
 import uncore.util._
 import util._
 import Chisel.ImplicitConversions._
-import cde.{Parameters, Field}
+import config._
 
 trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
   val outerDataBeats = p(TLKey(p(TLId))).dataBeats

src/main/scala/rocket/idecode.scala

@@ -6,7 +6,7 @@ import Chisel._
 import Instructions._
 import uncore.constants.MemoryOpConstants._
 import ALU._
-import cde.Parameters
+import config._
 import util._
 import Chisel.ImplicitConversions._
 

src/main/scala/rocket/nbdcache.scala

@@ -11,7 +11,7 @@ import uncore.util._
 import diplomacy._
 import util._
 import Chisel.ImplicitConversions._
-import cde.{Parameters, Field}
+import config._
 
 case class DCacheConfig(
   nMSHRs: Int = 1,

src/main/scala/rocket/ptw.scala

@@ -7,7 +7,7 @@ import uncore.agents._
 import uncore.constants._
 import util._
 import Chisel.ImplicitConversions._
-import cde.{Parameters, Field}
+import config._
 
 class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {
   val prv = Bits(width = 2)

src/main/scala/rocket/rocc.scala

@@ -8,7 +8,7 @@ import uncore.constants._
 import uncore.agents.CacheName
 import util._
 import Chisel.ImplicitConversions._
-import cde.{Parameters, Field}
+import config._
 
 case object RoccMaxTaggedMemXacts extends Field[Int]
 case object RoccNMemChannels extends Field[Int]

src/main/scala/rocket/rocket.scala

@@ -9,7 +9,7 @@ import uncore.constants._
 import junctions.HasAddrMapParameters
 import util._
 import Chisel.ImplicitConversions._
-import cde.{Parameters, Field}
+import config._
 
 case object XLen extends Field[Int]
 case object FetchWidth extends Field[Int]

src/main/scala/rocket/rvc.scala

@@ -3,7 +3,7 @@ package rocket
 import Chisel._
 import Chisel.ImplicitConversions._
 import util._
-import cde.Parameters
+import config._
 
 class ExpandedInstruction extends Bundle {
   val bits = UInt(width = 32)

src/main/scala/rocket/tile.scala

@@ -10,7 +10,7 @@ import uncore.agents._
 import uncore.converters._
 import uncore.devices._
 import util._
-import cde.{Parameters, Field}
+import config._
 import scala.collection.mutable.ListBuffer
 
 case object BuildRoCC extends Field[Seq[RoccParameters]]

src/main/scala/rocket/tlb.scala

@@ -7,7 +7,7 @@ import util._
 import Chisel.ImplicitConversions._
 import junctions._
 import scala.math._
-import cde.{Parameters, Field}
+import config._
 import uncore.agents._
 import uncore.coherence._