riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

make MultiChannel routing more performant

Browse Source
This commit is contained in:
Howard Mao 2015-11-18 17:06:38 -08:00
parent ea8ba49805
commit 379d43d5f4
1 changed files with 6 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/main/scala/RocketChip.scala
View File

@ -233,8 +233,12 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
println(f"\t$name%s $base%x - ${base + size - 1}%x")
}
val interconnect = Module(new NastiRecursiveInterconnect(
nMasters, nSlaves, addrMap)(p))
val interconnect = if (nMemChannels == 1)
Module(new NastiRecursiveInterconnect(
nMasters, nSlaves, addrMap))
else
Module(new NastiPerformanceInterconnect(
nBanksPerMemChannel, nMemChannels, 1, nSlaves - nMemChannels, addrMap))
for ((bank, i) <- managerEndpoints.zipWithIndex) {
val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))