From 379d43d5f4b02c5518ed1f7a1a9b4f44fc86a216 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Wed, 18 Nov 2015 17:06:38 -0800
Subject: [PATCH] make MultiChannel routing more performant

---
 src/main/scala/RocketChip.scala | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 45a5f7d6..6299c3e5 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -233,8 +233,12 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
     println(f"\t$name%s $base%x - ${base + size - 1}%x")
   }
 
-  val interconnect = Module(new NastiRecursiveInterconnect(
-    nMasters, nSlaves, addrMap)(p))
+  val interconnect = if (nMemChannels == 1)
+    Module(new NastiRecursiveInterconnect(
+      nMasters, nSlaves, addrMap))
+  else
+    Module(new NastiPerformanceInterconnect(
+      nBanksPerMemChannel, nMemChannels, 1, nSlaves - nMemChannels, addrMap))
 
   for ((bank, i) <- managerEndpoints.zipWithIndex) {
     val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))