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coreplex: move CacheCork in front of SBus

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Continue to not allow caches to cache ROMs.
Update TinyConfig and WithStatelessBridge.
This commit is contained in:
Henry Cook 2017-10-10 16:24:32 -07:00
parent 8f5f80f958
commit 37406706b4
4 changed files with 33 additions and 34 deletions
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17
src/main/scala/coreplex/Configs.scala
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@ -71,10 +71,9 @@ class WithNSmallCores(n: Int) extends Config((site, here, up) => {
}
})
class WithNTinyCores(n: Int) extends Config((site, here, up) => {
class With1TinyCore extends Config((site, here, up) => {
case XLen => 32
case RocketTilesKey => {
val tiny = RocketTileParams(
case RocketTilesKey => List(RocketTileParams(
core = RocketCoreParams(
useVM = false,
fpu = None,
@ -93,9 +92,11 @@ class WithNTinyCores(n: Int) extends Config((site, here, up) => {
nSets = 64,
nWays = 1,
nTLBEntries = 4,
blockBytes = site(CacheBlockBytes))))
List.tabulate(n)(i => tiny.copy(hartid = i))
}
blockBytes = site(CacheBlockBytes)))))
case RocketCrossingKey => List(RocketCrossingParams(
crossingType = SynchronousCrossing(),
master = TileMasterPortParams(cork = Some(true))
))
})
class WithNBanksPerMemChannel(n: Int) extends Config((site, here, up) => {
@ -153,10 +154,8 @@ class WithBufferlessBroadcastHub extends Config((site, here, up) => {
class WithStatelessBridge extends Config((site, here, up) => {
case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = { coreplex =>
implicit val p = coreplex.p
val cork = LazyModule(new TLCacheCork(unsafe = true))
val ww = LazyModule(new TLWidthWidget(coreplex.sbusBeatBytes))
ww.node :*= cork.node
(cork.node, ww.node, () => None)
(ww.node, ww.node, () => None)
})
})

4
src/main/scala/coreplex/RocketCoreplex.scala
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@ -17,13 +17,13 @@ case class TLNodeChain(in: TLInwardNode, out: TLOutwardNode)
case class TileMasterPortParams(
addBuffers: Int = 0,
blockerCtrlAddr: Option[BigInt] = None,
cork: Boolean = false) {
cork: Option[Boolean] = None) {
def adapterChain(coreplex: HasPeripheryBus)
(implicit p: Parameters): () => TLNodeChain = {
val blockerParams = blockerCtrlAddr.map(BusBlockerParams(_, coreplex.pbus.beatBytes, coreplex.sbus.beatBytes, 1))
val tile_master_cork = cork.option(LazyModule(new TLCacheCork))
val tile_master_cork = cork.map(u => (LazyModule(new TLCacheCork(unsafe = u))))
val tile_master_blocker = blockerParams.map(bp => LazyModule(new BusBlocker(bp)))
val tile_master_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
val tile_master_buffer = LazyModule(new TLBufferChain(addBuffers))

2
src/main/scala/system/Configs.scala
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@ -66,7 +66,7 @@ class DualCoreConfig extends Config(
class TinyConfig extends Config(
new WithNMemoryChannels(0) ++
new WithStatelessBridge ++
new WithNTinyCores(1) ++
new With1TinyCore ++
new BaseConfig)
class DefaultFPGAConfig extends Config(new BaseConfig)

4
src/main/scala/tilelink/CacheCork.scala
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@ -19,8 +19,8 @@ class TLCacheCork(unsafe: Boolean = false)(implicit p: Parameters) extends LazyM
managerFn = { case mp =>
mp.copy(
endSinkId = 1,
managers = mp.managers.map { m => m.copy(
supportsAcquireB = if (m.regionType == RegionType.UNCACHED) m.supportsGet else m.supportsAcquireB,
managers = mp.managers.map { m => m.copy( // Rocket requires m.supportsAcquireT || !m.supportsAcquireB, so, don't cache ROMs
supportsAcquireB = if (m.regionType == RegionType.UNCACHED && m.supportsPutFull) m.supportsGet else m.supportsAcquireB,
supportsAcquireT = if (m.regionType == RegionType.UNCACHED) m.supportsPutFull else m.supportsAcquireT)})})
lazy val module = new LazyModuleImp(this) {