131 lines
5.2 KiB
Scala
131 lines
5.2 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import scala.math.{min,max}
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import TLMessages._
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class TLCacheCork(unsafe: Boolean = false)(implicit p: Parameters) extends LazyModule
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{
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val node = TLAdapterNode(
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clientFn = { case cp =>
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cp.copy(clients = cp.clients.map { c => c.copy(
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supportsProbe = TransferSizes.none,
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sourceId = IdRange(c.sourceId.start*2, c.sourceId.end*2))})},
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managerFn = { case mp =>
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mp.copy(
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endSinkId = 1,
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managers = mp.managers.map { m => m.copy( // Rocket requires m.supportsAcquireT || !m.supportsAcquireB, so, don't cache ROMs
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supportsAcquireB = if (m.regionType == RegionType.UNCACHED && m.supportsPutFull) m.supportsGet else m.supportsAcquireB,
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supportsAcquireT = if (m.regionType == RegionType.UNCACHED) m.supportsPutFull else m.supportsAcquireT)})})
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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val clients = edgeIn.client.clients
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val caches = clients.filter(_.supportsProbe)
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require (clients.size == 1 || caches.size == 0 || unsafe, "Only one client can safely use a TLCacheCork")
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require (caches.size <= 1 || unsafe, "Only one caching client allowed")
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edgeOut.manager.managers.foreach { case m =>
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require (!m.supportsAcquireB || unsafe, "Cannot support caches beyond the Cork")
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require (m.regionType <= RegionType.UNCACHED)
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}
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// The Cork turns [Acquire=>Get] => [AccessAckData=>GrantData]
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// and [ReleaseData=>PutFullData] => [AccessAck=>ReleaseAck]
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// We need to encode information sufficient to reverse the transformation in output.
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// A caveat is that we get Acquire+Release with the same source and must keep the
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// source unique after transformation onto the A channel.
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// The coding scheme is:
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// Put: 1, Release: 0 => AccessAck
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// *: 0, Acquire: 1 => AccessAckData
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// Take requests from A to A or D (if BtoT Acquire)
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val a_a = Wire(out.a)
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val a_d = Wire(in.d)
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val isPut = in.a.bits.opcode === PutFullData || in.a.bits.opcode === PutPartialData
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val toD = (in.a.bits.opcode === AcquireBlock && in.a.bits.param === TLPermissions.BtoT) ||
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(in.a.bits.opcode === AcquirePerm)
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in.a.ready := Mux(toD, a_d.ready, a_a.ready)
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a_a.valid := in.a.valid && !toD
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a_a.bits := in.a.bits
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a_a.bits.source := in.a.bits.source << 1 | Mux(isPut, UInt(1), UInt(0))
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// Transform Acquire into Get
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when (in.a.bits.opcode === AcquireBlock || in.a.bits.opcode === AcquirePerm) {
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a_a.bits.opcode := Get
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a_a.bits.param := UInt(0)
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a_a.bits.source := in.a.bits.source << 1 | UInt(1)
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}
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// Upgrades are instantly successful
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a_d.valid := in.a.valid && toD
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a_d.bits := edgeIn.Grant(
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fromSink = UInt(0),
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toSource = in.a.bits.source,
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lgSize = in.a.bits.size,
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capPermissions = TLPermissions.toT)
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// Take ReleaseData from C to A; Release from C to D
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val c_a = Wire(out.a)
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c_a.valid := in.c.valid && in.c.bits.opcode === ReleaseData
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c_a.bits := edgeOut.Put(
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fromSource = in.c.bits.source << 1,
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toAddress = in.c.bits.address,
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lgSize = in.c.bits.size,
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data = in.c.bits.data)._2
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// Releases without Data succeed instantly
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val c_d = Wire(in.d)
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c_d.valid := in.c.valid && in.c.bits.opcode === Release
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c_d.bits := edgeIn.ReleaseAck(in.c.bits)
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assert (!in.c.valid || in.c.bits.opcode === Release || in.c.bits.opcode === ReleaseData)
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in.c.ready := Mux(in.c.bits.opcode === Release, c_d.ready, c_a.ready)
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// Discard E
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in.e.ready := Bool(true)
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// Block B; should never happen
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out.b.ready := Bool(false)
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assert (!out.b.valid)
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// Take responses from D and transform them
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val d_d = Wire(in.d)
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d_d <> out.d
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d_d.bits.source := out.d.bits.source >> 1
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when (out.d.bits.opcode === AccessAckData && out.d.bits.source(0)) {
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d_d.bits.opcode := GrantData
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d_d.bits.param := TLPermissions.toT
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}
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when (out.d.bits.opcode === AccessAck && !out.d.bits.source(0)) {
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d_d.bits.opcode := ReleaseAck
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}
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// Combine the sources of messages into the channels
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TLArbiter(TLArbiter.lowestIndexFirst)(out.a, (edgeOut.numBeats1(c_a.bits), c_a), (edgeOut.numBeats1(a_a.bits), a_a))
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TLArbiter(TLArbiter.lowestIndexFirst)(in.d, (edgeIn .numBeats1(d_d.bits), d_d), (UInt(0), Queue(c_d, 2)), (UInt(0), Queue(a_d, 2)))
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// Tie off unused ports
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in.b.valid := Bool(false)
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out.c.valid := Bool(false)
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out.e.valid := Bool(false)
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}
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}
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}
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object TLCacheCork
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{
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// applied to the TL source node; y.node := TLCacheCork()(x.node)
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def apply(unsafe: Boolean = false)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
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val cork = LazyModule(new TLCacheCork(unsafe))
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cork.node :=? x
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cork.node
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}
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}
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