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coreplex: move CacheCork in front of SBus

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Continue to not allow caches to cache ROMs.
Update TinyConfig and WithStatelessBridge.
This commit is contained in:
Henry Cook 2017-10-10 16:24:32 -07:00
parent 8f5f80f958
commit 37406706b4
4 changed files with 33 additions and 34 deletions
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55
src/main/scala/coreplex/Configs.scala
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@ -71,31 +71,32 @@ class WithNSmallCores(n: Int) extends Config((site, here, up) => {
} }
}) })
class WithNTinyCores(n: Int) extends Config((site, here, up) => { class With1TinyCore extends Config((site, here, up) => {
case XLen => 32 case XLen => 32
case RocketTilesKey => { case RocketTilesKey => List(RocketTileParams(
val tiny = RocketTileParams( core = RocketCoreParams(
core = RocketCoreParams( useVM = false,
useVM = false, fpu = None,
fpu = None, mulDiv = Some(MulDivParams(mulUnroll = 8))),
mulDiv = Some(MulDivParams(mulUnroll = 8))), btb = None,
btb = None, dcache = Some(DCacheParams(
dcache = Some(DCacheParams( rowBits = site(SystemBusKey).beatBits,
rowBits = site(SystemBusKey).beatBits, nSets = 256, // 16Kb scratchpad
nSets = 256, // 16Kb scratchpad nWays = 1,
nWays = 1, nTLBEntries = 4,
nTLBEntries = 4, nMSHRs = 0,
nMSHRs = 0, blockBytes = site(CacheBlockBytes),
blockBytes = site(CacheBlockBytes), scratch = Some(0x80000000L))),
scratch = Some(0x80000000L))), icache = Some(ICacheParams(
icache = Some(ICacheParams( rowBits = site(SystemBusKey).beatBits,
rowBits = site(SystemBusKey).beatBits, nSets = 64,
nSets = 64, nWays = 1,
nWays = 1, nTLBEntries = 4,
nTLBEntries = 4, blockBytes = site(CacheBlockBytes)))))
blockBytes = site(CacheBlockBytes)))) case RocketCrossingKey => List(RocketCrossingParams(
List.tabulate(n)(i => tiny.copy(hartid = i)) crossingType = SynchronousCrossing(),
} master = TileMasterPortParams(cork = Some(true))
))
}) })
class WithNBanksPerMemChannel(n: Int) extends Config((site, here, up) => { class WithNBanksPerMemChannel(n: Int) extends Config((site, here, up) => {
@ -153,10 +154,8 @@ class WithBufferlessBroadcastHub extends Config((site, here, up) => {
class WithStatelessBridge extends Config((site, here, up) => { class WithStatelessBridge extends Config((site, here, up) => {
case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = { coreplex => case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = { coreplex =>
implicit val p = coreplex.p implicit val p = coreplex.p
val cork = LazyModule(new TLCacheCork(unsafe = true))
val ww = LazyModule(new TLWidthWidget(coreplex.sbusBeatBytes)) val ww = LazyModule(new TLWidthWidget(coreplex.sbusBeatBytes))
ww.node :*= cork.node (ww.node, ww.node, () => None)
(cork.node, ww.node, () => None)
}) })
}) })

4
src/main/scala/coreplex/RocketCoreplex.scala
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@ -17,13 +17,13 @@ case class TLNodeChain(in: TLInwardNode, out: TLOutwardNode)
case class TileMasterPortParams( case class TileMasterPortParams(
addBuffers: Int = 0, addBuffers: Int = 0,
blockerCtrlAddr: Option[BigInt] = None, blockerCtrlAddr: Option[BigInt] = None,
cork: Boolean = false) { cork: Option[Boolean] = None) {
def adapterChain(coreplex: HasPeripheryBus) def adapterChain(coreplex: HasPeripheryBus)
(implicit p: Parameters): () => TLNodeChain = { (implicit p: Parameters): () => TLNodeChain = {
val blockerParams = blockerCtrlAddr.map(BusBlockerParams(_, coreplex.pbus.beatBytes, coreplex.sbus.beatBytes, 1)) val blockerParams = blockerCtrlAddr.map(BusBlockerParams(_, coreplex.pbus.beatBytes, coreplex.sbus.beatBytes, 1))
val tile_master_cork = cork.option(LazyModule(new TLCacheCork)) val tile_master_cork = cork.map(u => (LazyModule(new TLCacheCork(unsafe = u))))
val tile_master_blocker = blockerParams.map(bp => LazyModule(new BusBlocker(bp))) val tile_master_blocker = blockerParams.map(bp => LazyModule(new BusBlocker(bp)))
val tile_master_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable)) val tile_master_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
val tile_master_buffer = LazyModule(new TLBufferChain(addBuffers)) val tile_master_buffer = LazyModule(new TLBufferChain(addBuffers))

2
src/main/scala/system/Configs.scala
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@ -66,7 +66,7 @@ class DualCoreConfig extends Config(
class TinyConfig extends Config( class TinyConfig extends Config(
new WithNMemoryChannels(0) ++ new WithNMemoryChannels(0) ++
new WithStatelessBridge ++ new WithStatelessBridge ++
new WithNTinyCores(1) ++ new With1TinyCore ++
new BaseConfig) new BaseConfig)
class DefaultFPGAConfig extends Config(new BaseConfig) class DefaultFPGAConfig extends Config(new BaseConfig)

6
src/main/scala/tilelink/CacheCork.scala
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@ -19,9 +19,9 @@ class TLCacheCork(unsafe: Boolean = false)(implicit p: Parameters) extends LazyM
managerFn = { case mp => managerFn = { case mp =>
mp.copy( mp.copy(
endSinkId = 1, endSinkId = 1,
managers = mp.managers.map { m => m.copy( managers = mp.managers.map { m => m.copy( // Rocket requires m.supportsAcquireT || !m.supportsAcquireB, so, don't cache ROMs
supportsAcquireB = if (m.regionType == RegionType.UNCACHED) m.supportsGet else m.supportsAcquireB, supportsAcquireB = if (m.regionType == RegionType.UNCACHED && m.supportsPutFull) m.supportsGet else m.supportsAcquireB,
supportsAcquireT = if (m.regionType == RegionType.UNCACHED) m.supportsPutFull else m.supportsAcquireT)})}) supportsAcquireT = if (m.regionType == RegionType.UNCACHED) m.supportsPutFull else m.supportsAcquireT)})})
lazy val module = new LazyModuleImp(this) { lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>