riscv/rocket-chip
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CacheName no longer needed in RoCCInterface

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With dcacheParams passed to a RoCC, the CacheName no longer needs to be
specified.
This commit is contained in:
Schuyler Eldridge 2016-11-29 21:49:40 -05:00 committed by Henry Cook
parent 624db2034b
commit 36fe024671
1 changed files with 2 additions and 2 deletions
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2
src/main/scala/rocket/rocc.scala
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@ -42,7 +42,7 @@ class RoCCResponse(implicit p: Parameters) extends CoreBundle()(p) {
class RoCCInterface(implicit p: Parameters) extends CoreBundle()(p) { class RoCCInterface(implicit p: Parameters) extends CoreBundle()(p) {
val cmd = Decoupled(new RoCCCommand).flip val cmd = Decoupled(new RoCCCommand).flip
val resp = Decoupled(new RoCCResponse) val resp = Decoupled(new RoCCResponse)
val mem = new HellaCacheIO()(p.alterPartial({ case CacheName => CacheName("L1D") })) val mem = new HellaCacheIO
val busy = Bool(OUTPUT) val busy = Bool(OUTPUT)
val interrupt = Bool(OUTPUT) val interrupt = Bool(OUTPUT)