riscv/rocket-chip
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Adjust Verilog testbench to use new debug_stats_pcr signal that has been exported to the top level. It is the or-reduction of the stats pcr for each core. Push rocket (export stats pcr to top level). This scheme is cleaner than digging into the hierarchy.

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This commit is contained in:
Stephen Twigg 2013-09-25 01:21:41 -07:00
parent eb7e6f03b3
commit 36dfff5ee8
2 changed files with 4 additions and 1 deletions
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2
rocket

@ -1 +1 @@
Subproject commit 6eb17f7720c040c373cf9003dea4be874dab50a7 Subproject commit 8b7ca87f102c42ce9fdc3a8559b4798d2833e676

3
src/main/scala/RocketChip.scala
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@ -212,6 +212,8 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf
hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htif_width), Bool(true), htif.io.host.in.ready) hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htif_width), Bool(true), htif.io.host.in.ready)
io.host.clk := hio.io.clk_slow io.host.clk := hio.io.clk_slow
io.host.clk_edge := Reg(next=io.host.clk && !Reg(next=io.host.clk)) io.host.clk_edge := Reg(next=io.host.clk && !Reg(next=io.host.clk))
io.host.debug_stats_pcr := htif.io.host.debug_stats_pcr
} }
class TopIO(htifWidth: Int) extends Bundle { class TopIO(htifWidth: Int) extends Bundle {
@ -276,6 +278,7 @@ class Top extends Module {
hl.pcr_rep <> Queue(tile.io.host.pcr_rep, 1) hl.pcr_rep <> Queue(tile.io.host.pcr_rep, 1)
hl.ipi_req <> Queue(tile.io.host.ipi_req, 1) hl.ipi_req <> Queue(tile.io.host.ipi_req, 1)
tile.io.host.ipi_rep <> Queue(hl.ipi_rep, 1) tile.io.host.ipi_rep <> Queue(hl.ipi_rep, 1)
hl.debug_stats_pcr := tile.io.host.debug_stats_pcr
} }
io.host <> uncore.io.host io.host <> uncore.io.host