From 36dfff5ee8b27f13cf7867819a14ab57c4277d5c Mon Sep 17 00:00:00 2001 From: Stephen Twigg Date: Wed, 25 Sep 2013 01:21:41 -0700 Subject: [PATCH] Adjust Verilog testbench to use new debug_stats_pcr signal that has been exported to the top level. It is the or-reduction of the stats pcr for each core. Push rocket (export stats pcr to top level). This scheme is cleaner than digging into the hierarchy. --- rocket | 2 +- src/main/scala/RocketChip.scala | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/rocket b/rocket index 6eb17f77..8b7ca87f 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 6eb17f7720c040c373cf9003dea4be874dab50a7 +Subproject commit 8b7ca87f102c42ce9fdc3a8559b4798d2833e676 diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 1577df10..d282d2b0 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -212,6 +212,8 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htif_width), Bool(true), htif.io.host.in.ready) io.host.clk := hio.io.clk_slow io.host.clk_edge := Reg(next=io.host.clk && !Reg(next=io.host.clk)) + + io.host.debug_stats_pcr := htif.io.host.debug_stats_pcr } class TopIO(htifWidth: Int) extends Bundle { @@ -276,6 +278,7 @@ class Top extends Module { hl.pcr_rep <> Queue(tile.io.host.pcr_rep, 1) hl.ipi_req <> Queue(tile.io.host.ipi_req, 1) tile.io.host.ipi_rep <> Queue(hl.ipi_rep, 1) + hl.debug_stats_pcr := tile.io.host.debug_stats_pcr } io.host <> uncore.io.host