moved exception handling from ex stage in dpath to mem stage in ctrl

2011-11-10 00:50:09 -08:00
parent fbfa356d2a
commit 36aa4bcc9d
7 changed files with 153 additions and 143 deletions
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@ -51,11 +51,9 @@ class rocketSRAMsp(entries: Int, width: Int) extends Component {
 }

 // basic direct mapped instruction cache
+// 32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines
 // parameters :
 //    lines = # cache lines
-//    addr_bits = address width (word addressable) bits
-//    32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines
-
 class rocketICacheDM(lines: Int) extends Component {
  val io = new ioICacheDM();