moved exception handling from ex stage in dpath to mem stage in ctrl
This commit is contained in:
Rimas Avizienis
@ -33,17 +33,11 @@ class ioCtrlDpath extends Bundle()
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val sel_wb = UFix(3, 'output);
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val ren_pcr = Bool('output);
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val wen_pcr = Bool('output);
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// FIXME: move exception handling stuff (generating cause value, etc)
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// from EX stage of dpath to MEM stage of control
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val xcpt_illegal = Bool('output);
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val xcpt_privileged = Bool('output);
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val xcpt_fpu = Bool('output);
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val xcpt_syscall = Bool('output);
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// val xcpt_dtlb = Bool('output);
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val xcpt_itlb = Bool('output);
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val exception = Bool('output);
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val cause = UFix(5,'output);
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val eret = Bool('output);
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val mem_load = Bool('output);
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val wen = Bool('output);
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val wen = Bool('output);
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// inputs from datapath
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val btb_hit = Bool('input);
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val inst = Bits(32, 'input);
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@ -53,10 +47,9 @@ class ioCtrlDpath extends Bundle()
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val div_rdy = Bool('input);
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val div_result_val = Bool('input);
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val mul_result_val = Bool('input);
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val ex_waddr = UFix(5,'input); // write addr from execute stage
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val ex_waddr = UFix(5,'input); // write addr from execute stage
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val mem_waddr = UFix(5,'input); // write addr from memory stage
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val wb_waddr = UFix(5,'input); // write addr from writeback stage
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val exception = Bool('input);
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val wb_waddr = UFix(5,'input); // write addr from writeback stage
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val status = Bits(17, 'input);
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val sboard_clr0 = Bool('input);
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val sboard_clr0a = UFix(5, 'input);
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@ -71,8 +64,10 @@ class ioCtrlAll extends Bundle()
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val imem = new ioImem(List("req_val", "req_rdy", "resp_val")).flip();
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val dmem = new ioDmem(List("req_val", "req_rdy", "req_cmd", "req_type", "resp_miss")).flip();
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val host = new ioHost(List("start"));
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val dtlb_xcpt = Bool('input);
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val itlb_xcpt = Bool('input);
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val dtlb_miss = Bool('input);
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val xcpt_dtlb_ld = Bool('input);
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val xcpt_dtlb_st = Bool('input);
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val xcpt_itlb = Bool('input);
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}
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class rocketCtrl extends Component
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@ -97,6 +92,7 @@ class rocketCtrl extends Component
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JALR_C-> List(Y, BR_JR, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,N,N,N,N),
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JALR_J-> List(Y, BR_JR, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,N,N,N,N),
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JALR_R-> List(Y, BR_JR, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,N,N,N,N),
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RDNPC-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,N,N,N,N),
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LB-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_B, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,N,N,N,N),
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LH-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XRD, MT_H, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,N,N,N,N),
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@ -189,9 +185,6 @@ class rocketCtrl extends Component
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AMOMAX_D-> List(xpr64, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_MAX, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,N,N,N,N),
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AMOMINU_D->List(xpr64, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_MINU,MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,N,N,N,N),
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AMOMAXU_D->List(xpr64, BR_N, REN_Y,REN_Y,A2_0, A1_RS1,DW_XPR,FN_ADD, M_Y,M_XA_MAXU,MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,N,N,N,N),
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// miscellaneous
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RDNPC-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,N,N,N,N),
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*/
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));
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@ -210,7 +203,7 @@ class rocketCtrl extends Component
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io.console.valid := console_out_fire.toBool;
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val wb_reg_div_mul_val = Reg(){Bool()};
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val dcache_miss = Reg(){Bool()};
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val dcache_miss = Reg(io.dmem.resp_miss);
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val sboard = new rocketCtrlSboard();
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sboard.io.raddra := id_raddr2.toUFix;
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@ -232,7 +225,8 @@ class rocketCtrl extends Component
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val id_stall_ra = sboard.io.stallra;
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val id_reg_btb_hit = Reg(resetVal = Bool(false));
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val id_reg_itlb_xcpt = Reg(resetVal = Bool(false));
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val id_reg_xcpt_itlb = Reg(resetVal = Bool(false));
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val ex_reg_br_type = Reg(){UFix(width = 4)};
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val ex_reg_btb_hit = Reg(){Bool()};
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val ex_reg_div_mul_val = Reg(){Bool()};
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@ -241,15 +235,27 @@ class rocketCtrl extends Component
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val ex_reg_mem_type = Reg(){UFix(width = 3)};
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val ex_reg_eret = Reg(resetVal = Bool(false));
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val ex_reg_privileged = Reg(resetVal = Bool(false));
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// val ex_reg_itlb_xcpt = Reg(resetVal = Bool(false));
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val ex_reg_xcpt_itlb = Reg(resetVal = Bool(false));
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val ex_reg_xcpt_illegal = Reg(resetVal = Bool(false));
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val ex_reg_xcpt_privileged = Reg(resetVal = Bool(false));
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// val ex_reg_xcpt_fpu = Reg(resetVal = Bool(false));
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val ex_reg_xcpt_syscall = Reg(resetVal = Bool(false));
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val mem_reg_xcpt_itlb = Reg(resetVal = Bool(false));
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val mem_reg_xcpt_illegal = Reg(resetVal = Bool(false));
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val mem_reg_xcpt_privileged = Reg(resetVal = Bool(false));
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// val mem_reg_xcpt_fpu = Reg(resetVal = Bool(false));
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val mem_reg_xcpt_fpu = Bool(false); // FIXME: trap on unimplemented FPU instructions
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val mem_reg_xcpt_syscall = Reg(resetVal = Bool(false));
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when (!io.dpath.stalld) {
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when (io.dpath.killf) {
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id_reg_itlb_xcpt <== Bool(false);
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id_reg_xcpt_itlb <== Bool(false);
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id_reg_btb_hit <== Bool(false);
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}
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otherwise{
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id_reg_itlb_xcpt <== io.itlb_xcpt;
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id_reg_xcpt_itlb <== io.xcpt_itlb;
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id_reg_btb_hit <== io.dpath.btb_hit;
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}
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}
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@ -263,7 +269,12 @@ class rocketCtrl extends Component
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ex_reg_mem_type <== UFix(0, 3);
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ex_reg_eret <== Bool(false);
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ex_reg_privileged <== Bool(false);
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// ex_reg_itlb_xcpt <== Bool(false);
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ex_reg_xcpt_itlb <== Bool(false);
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ex_reg_xcpt_illegal <== Bool(false);
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ex_reg_xcpt_privileged <== Bool(false);
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// ex_reg_xcpt_fpu <== Bool(false);
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ex_reg_xcpt_syscall <== Bool(false);
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}
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otherwise {
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ex_reg_br_type <== id_br_type;
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@ -274,7 +285,12 @@ class rocketCtrl extends Component
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ex_reg_mem_type <== id_mem_type;
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ex_reg_eret <== id_eret.toBool;
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ex_reg_privileged <== id_privileged.toBool;
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// ex_reg_itlb_xcpt <== id_reg_itlb_xcpt;
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ex_reg_xcpt_itlb <== id_reg_xcpt_itlb;
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ex_reg_xcpt_illegal <== ~id_int_val.toBool;
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ex_reg_xcpt_privileged <== (id_privileged & ~io.dpath.status(5)).toBool;
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// ex_reg_xcpt_fpu <== Bool(false);
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ex_reg_xcpt_syscall <== id_syscall.toBool;
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}
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val beq = io.dpath.br_eq;
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@ -316,6 +332,12 @@ class rocketCtrl extends Component
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mem_reg_mem_cmd <== UFix(0, 4);
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mem_reg_mem_type <== UFix(0, 3);
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mem_reg_privileged <== Bool(false);
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mem_reg_xcpt_itlb <== Bool(false);
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mem_reg_xcpt_illegal <== Bool(false);
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mem_reg_xcpt_privileged <== Bool(false);
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// mem_reg_xcpt_fpu <== Bool(false);
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mem_reg_xcpt_syscall <== Bool(false);
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}
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otherwise {
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mem_reg_div_mul_val <== ex_reg_div_mul_val;
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@ -324,6 +346,12 @@ class rocketCtrl extends Component
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mem_reg_mem_cmd <== ex_reg_mem_cmd;
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mem_reg_mem_type <== ex_reg_mem_type;
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mem_reg_privileged <== ex_reg_privileged;
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mem_reg_xcpt_itlb <== ex_reg_xcpt_itlb;
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mem_reg_xcpt_illegal <== mem_reg_xcpt_illegal;
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mem_reg_xcpt_privileged <== ex_reg_xcpt_privileged;
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// mem_reg_xcpt_fpu <== Bool(false);
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mem_reg_xcpt_syscall <== ex_reg_xcpt_syscall;
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}
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when (reset.toBool || io.dpath.killm) {
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@ -333,31 +361,54 @@ class rocketCtrl extends Component
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wb_reg_div_mul_val <== mem_reg_div_mul_val;
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}
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// replay execute stage PC when the D$ is blocked
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val replay_ex = ex_reg_mem_val && !io.dmem.req_rdy;
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// replay execute stage PC on a D$ load miss
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val mem_cmd_load = mem_reg_mem_val && (mem_reg_mem_cmd === M_XRD);
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val replay_mem = io.dmem.resp_miss;
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val kill_ex = replay_ex | replay_mem | mem_reg_privileged;
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val kill_mem = io.dpath.exception; // TODO: add load/store related exceptions
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// exception handling
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val mem_exception =
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io.xcpt_dtlb_ld ||
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io.xcpt_dtlb_st ||
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mem_reg_xcpt_illegal ||
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mem_reg_xcpt_privileged ||
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mem_reg_xcpt_fpu ||
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mem_reg_xcpt_syscall ||
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mem_reg_xcpt_itlb;
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val mem_cause =
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// instruction address misaligned
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Mux(mem_reg_xcpt_itlb, UFix(1,5), // instruction access fault
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Mux(mem_reg_xcpt_illegal, UFix(2,5), // illegal instruction
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Mux(mem_reg_xcpt_privileged, UFix(3,5), // privileged instruction
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Mux(mem_reg_xcpt_fpu, UFix(4,5), // FPU disabled
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// interrupt
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Mux(mem_reg_xcpt_syscall, UFix(6,5), // system call
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// breakpoint
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// misaligned load
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// misaligned store
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Mux(io.xcpt_dtlb_ld, UFix(8,5), // load fault
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Mux(io.xcpt_dtlb_st, UFix(9,5), // store fault
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UFix(0,5))))))));
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// write cause to PCR on an exception
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io.dpath.exception := mem_exception;
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io.dpath.cause := mem_cause;
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dcache_miss <== io.dmem.resp_miss;
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// replay execute stage PC when the D$ is blocked, when the D$ misses, and for privileged instructions
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val replay_ex = (ex_reg_mem_val && !io.dmem.req_rdy) || io.dmem.resp_miss || mem_reg_privileged;
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io.dpath.mem_load := mem_cmd_load;
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// FIXME: dtlb exception handling broken, need to move cause value generation
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// to mem stage. also should probably move it from dpath to ctrl
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// replay mem stage PC on a DTLB miss
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val replay_mem = io.dtlb_miss;
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val kill_ex = replay_ex || replay_mem;
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val kill_mem = mem_exception || io.dtlb_miss;
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io.dpath.sel_pc :=
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Mux(io.dpath.exception || io.dtlb_xcpt || mem_reg_eret, PC_PCR,
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Mux(replay_ex || replay_mem || mem_reg_privileged, PC_EX,
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Mux(!ex_reg_btb_hit && br_taken, PC_BR,
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Mux(ex_reg_btb_hit && !br_taken, PC_EX4,
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Mux(jr_taken, PC_JR,
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Mux(j_taken, PC_J,
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Mux(io.dpath.btb_hit, PC_BTB,
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PC_4)))))));
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Mux(mem_exception, PC_EVEC, // exception
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Mux(replay_mem, PC_MEM, // dtlb miss
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Mux(mem_reg_eret, PC_PCR, // eret instruction
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Mux(replay_ex, PC_EX, // D$ blocked, D$ miss, privileged inst
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Mux(!ex_reg_btb_hit && br_taken, PC_BR, // mispredicted taken branch
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Mux(ex_reg_btb_hit && !br_taken, PC_EX4, // mispredicted not taken branch
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Mux(jr_taken, PC_JR, // jump register
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Mux(j_taken, PC_J, // jump
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Mux(io.dpath.btb_hit, PC_BTB, // predicted PC from BTB
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PC_4))))))))); // PC+4
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io.dpath.wen_btb := ~ex_reg_btb_hit & br_taken & ~kill_ex & ~kill_mem;
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@ -366,8 +417,7 @@ class rocketCtrl extends Component
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ex_reg_btb_hit & ~br_taken |
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jr_taken |
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j_taken |
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io.dpath.exception |
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mem_reg_privileged |
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mem_exception |
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mem_reg_eret |
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replay_ex |
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replay_mem;
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@ -451,6 +501,7 @@ class rocketCtrl extends Component
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io.dpath.killx := kill_ex.toBool || kill_mem.toBool;
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io.dpath.killm := kill_mem.toBool;
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io.dpath.mem_load := mem_reg_mem_val && (mem_reg_mem_cmd === M_XRD);
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io.dpath.ren2 := id_ren2.toBool;
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io.dpath.ren1 := id_ren1.toBool;
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io.dpath.sel_alu2 := id_sel_alu2;
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@ -469,12 +520,6 @@ class rocketCtrl extends Component
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io.dpath.ren_pcr := id_ren_pcr.toBool;
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io.dpath.wen_pcr := id_wen_pcr.toBool;
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io.dpath.eret := id_eret.toBool;
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io.dpath.xcpt_illegal := ~id_int_val.toBool;
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io.dpath.xcpt_privileged := (id_privileged & ~io.dpath.status(5)).toBool;
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io.dpath.xcpt_fpu := Bool(false);
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io.dpath.xcpt_syscall := id_syscall.toBool;
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io.dpath.xcpt_itlb := id_reg_itlb_xcpt;
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}
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}
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Block a user