riscv/rocket-chip
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moved exception handling from ex stage in dpath to mem stage in ctrl

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This commit is contained in:
Rimas Avizienis
2011-11-10 00:50:09 -08:00
parent fbfa356d2a
commit 36aa4bcc9d
7 changed files with 153 additions and 143 deletions
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32
rocket/src/main/scala/cpu.scala
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@ -51,14 +51,11 @@ class rocketProc extends Component
val arb = new rocketDmemArbiter();
ctrl.io.dpath <> dpath.io.ctrl;
ctrl.io.host.start ^^ io.host.start;
// ctrl.io.dmem ^^ io.dmem;
// ctrl.io.imem ^^ io.imem;
// dpath.io.dmem ^^ io.dmem;
// dpath.io.imem.req_addr ^^ io.imem.req_addr;
dpath.io.imem.resp_data ^^ io.imem.resp_data;
dpath.io.host ^^ io.host;
ctrl.io.host.start := io.host.start;
dpath.io.debug ^^ io.debug;
// dpath.io.imem.resp_data ^^ io.imem.resp_data;
// FIXME: make this less verbose
// connect ITLB to I$, ctrl, dpath
@ -71,7 +68,8 @@ class rocketProc extends Component
io.imem.req_addr := itlb.io.cpu.resp_addr;
ctrl.io.imem.req_rdy := itlb.io.cpu.req_rdy && io.imem.req_rdy;
ctrl.io.imem.resp_val := io.imem.resp_val;
ctrl.io.itlb_xcpt := itlb.io.cpu.exception;
dpath.io.imem.resp_data := io.imem.resp_data;
ctrl.io.xcpt_itlb := itlb.io.cpu.exception;
// connect DTLB to D$ arbiter, ctrl+dpath
dtlb.io.cpu.invalidate := Bool(false); // FIXME
@ -80,7 +78,9 @@ class rocketProc extends Component
dtlb.io.cpu.req_cmd := ctrl.io.dmem.req_cmd;
dtlb.io.cpu.req_asid := Bits(0,ASID_BITS); // FIXME: connect to PCR
dtlb.io.cpu.req_addr := dpath.io.dmem.req_addr;
ctrl.io.dtlb_xcpt := dtlb.io.cpu.exception;
ctrl.io.xcpt_dtlb_ld := dtlb.io.cpu.xcpt_ld;
ctrl.io.xcpt_dtlb_st := dtlb.io.cpu.xcpt_st;
ctrl.io.dtlb_miss := dtlb.io.cpu.resp_miss;
// connect page table walker to TLBs, page table base register (from PCR)
// and D$ arbiter (selects between requests from pipeline and PTW, PTW has priority)
@ -90,8 +90,7 @@ class rocketProc extends Component
arb.io.ptw <> ptw.io.dmem;
arb.io.mem ^^ io.dmem
// FIXME: make this less verbose
// connect arbiter to ctrl+dpath
// connect arbiter to ctrl+dpath+DTLB
arb.io.cpu.req_val := dtlb.io.cpu.resp_val;
arb.io.cpu.req_cmd := ctrl.io.dmem.req_cmd;
arb.io.cpu.req_type := ctrl.io.dmem.req_type;
@ -104,19 +103,6 @@ class rocketProc extends Component
dpath.io.dmem.resp_tag := arb.io.cpu.resp_tag;
dpath.io.dmem.resp_data := arb.io.cpu.resp_data;
// arb.io.cpu.req_val := ctrl.io.dmem.req_val;
// arb.io.cpu.req_cmd := ctrl.io.dmem.req_cmd;
// arb.io.cpu.req_type := ctrl.io.dmem.req_type;
// arb.io.cpu.req_addr := dpath.io.dmem.req_addr;
// arb.io.cpu.req_data := dpath.io.dmem.req_data;
// arb.io.cpu.req_tag := dpath.io.dmem.req_tag;
// ctrl.io.dmem.req_rdy := arb.io.cpu.req_rdy;
// ctrl.io.dmem.resp_miss := arb.io.cpu.resp_miss;
// ctrl.io.dmem.resp_val := arb.io.cpu.resp_val;
// dpath.io.dmem.resp_val := arb.io.cpu.resp_val;
// dpath.io.dmem.resp_tag := arb.io.cpu.resp_tag;
// dpath.io.dmem.resp_data := arb.io.cpu.resp_data;
// FIXME: console disconnected
// io.console.bits := dpath.io.dpath.rs1(7,0);
io.console.bits := Bits(0,8);