riscv/rocket-chip
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Filled out 4 state coherence functions for cache

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This commit is contained in:
Henry Cook
2012-03-02 21:58:50 -08:00
parent 00989c58bd
commit 35f97bf858
2 changed files with 27 additions and 19 deletions
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rocket/src/main/scala/nbdcache.scala
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@ -605,8 +605,6 @@ abstract class HellaCache extends Component {
def newStateOnWriteback(): UFix
def newStateOnFlush(): UFix
def newStateOnHit(cmd: Bits, state: UFix): UFix
def newStateOnPrimaryMiss(cmd: Bits): UFix
def newStateOnSecondaryMiss(cmd: Bits, state: UFix): UFix
}
class HellaCacheUniproc extends HellaCache with ThreeStateIncoherence {