Correction to probe reply w/ data handling
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1e1926ce63
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@ -31,8 +31,7 @@ class HubMemReq extends Bundle {
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}
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class TrackerProbeData extends Bundle {
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val valid = Bool()
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val data_tile_id = Bits(width = log2up(NTILES))
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val tile_id = Bits(width = TILE_ID_BITS)
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}
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class TrackerAllocReq extends Bundle {
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@ -182,7 +181,7 @@ trait FourStateCoherence extends CoherencePolicy {
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class XactTracker(id: Int) extends Component with CoherencePolicy {
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val io = new Bundle {
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val alloc_req = (new ioDecoupled) { new TrackerAllocReq() }.flip
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val probe_data = (new TrackerProbeData).asInput
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val p_data = (new ioPipe) { new TrackerProbeData() }
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val can_alloc = Bool(INPUT)
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val xact_finish = Bool(INPUT)
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val p_rep_cnt_dec = Bits(NTILES, INPUT)
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@ -331,9 +330,9 @@ class XactTracker(id: Int) extends Component with CoherencePolicy {
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state := s_mem
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}
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}
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when(io.probe_data.valid) {
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when(io.p_data.valid) {
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p_rep_data_needs_write := Bool(true)
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p_rep_tile_id_ := io.p_rep_tile_id
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p_rep_tile_id_ := io.p_data.bits.tile_id
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}
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}
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is(s_mem) {
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@ -413,7 +412,9 @@ class CoherenceHubBroadcast extends CoherenceHub {
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val do_free_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
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val p_rep_cnt_dec_arr = VecBuf(NGLOBAL_XACTS){ Vec(NTILES){ Wire(){Bool()} } }
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val p_req_cnt_inc_arr = VecBuf(NGLOBAL_XACTS){ Vec(NTILES){ Wire(){Bool()} } }
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val sent_x_rep_ack_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
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val sent_x_rep_ack_arr = Vec(NGLOBAL_XACTS){ Wire(){ Bool()} }
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val p_data_tile_id_arr = Vec(NGLOBAL_XACTS){ Wire(){ Bits(width = TILE_ID_BITS)} }
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val p_data_valid_arr = Vec(NGLOBAL_XACTS){ Wire(){ Bool()} }
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for( i <- 0 until NGLOBAL_XACTS) {
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val t = trackerList(i).io
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@ -425,14 +426,18 @@ class CoherenceHubBroadcast extends CoherenceHub {
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sh_count_arr(i) := t.sharer_count
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send_x_rep_ack_arr(i) := t.send_x_rep_ack
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t.xact_finish := do_free_arr(i)
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t.p_data.bits.tile_id := p_data_tile_id_arr(i)
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t.p_data.valid := p_data_valid_arr(i)
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t.p_rep_cnt_dec := p_rep_cnt_dec_arr(i).toBits
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t.p_req_cnt_inc := p_req_cnt_inc_arr(i).toBits
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t.sent_x_rep_ack := sent_x_rep_ack_arr(i)
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do_free_arr(i) := Bool(false)
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sent_x_rep_ack_arr(i) := Bool(false)
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p_data_tile_id_arr(i) := Bits(0, width = TILE_ID_BITS)
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p_data_valid_arr(i) := Bool(false)
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for( j <- 0 until NTILES) {
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p_rep_cnt_dec_arr(i)(j) := Bool(false)
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p_req_cnt_inc_arr(i)(j) := Bool(false)
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p_rep_cnt_dec_arr(i)(j) := Bool(false)
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p_req_cnt_inc_arr(i)(j) := Bool(false)
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}
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}
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@ -490,7 +495,9 @@ class CoherenceHubBroadcast extends CoherenceHub {
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val p_rep_data = io.tiles(j).probe_rep_data
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val idx = p_rep.bits.global_xact_id
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p_rep.ready := foldR(trackerList.map(_.io.pop_p_rep(j)))(_ || _)
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p_rep_data.ready := foldR(trackerList.map(_.io.pop_p_rep_data(j)))(_ || _)
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p_rep_data.ready := foldR(trackerList.map(_.io.pop_p_rep_data(j)))(_ || _)
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p_data_valid_arr(idx) := p_rep.valid && p_rep.bits.has_data
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p_data_tile_id_arr(idx) := UFix(j)
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}
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for( i <- 0 until NGLOBAL_XACTS ) {
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trackerList(i).io.p_rep_data.valid := io.tiles(trackerList(i).io.p_rep_tile_id).probe_rep_data.valid
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