riscv/rocket-chip
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Use Vec.fill, not Vec.apply, for Vec literals

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Andrew Waterman 2015-08-27 10:00:43 -07:00
parent 94287fed90
commit 350d530766
1 changed files with 4 additions and 4 deletions
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8
uncore/src/main/scala/cache.scala
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@ -492,7 +492,7 @@ class L2VoluntaryReleaseTracker(trackerId: Int) extends L2XactTracker {
val state = Reg(init=s_idle) val state = Reg(init=s_idle)
val xact = Reg(Bundle(new ReleaseFromSrc, { case TLId => params(InnerTLId); case TLDataBits => 0 })) val xact = Reg(Bundle(new ReleaseFromSrc, { case TLId => params(InnerTLId); case TLDataBits => 0 }))
val data_buffer = Reg(init=Vec(UInt(0, width = innerDataBits), innerDataBeats)) val data_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits)))
val xact_way_en = Reg{ Bits(width = nWays) } val xact_way_en = Reg{ Bits(width = nWays) }
val xact_old_meta = Reg{ new L2Metadata } val xact_old_meta = Reg{ new L2Metadata }
val coh = xact_old_meta.coh val coh = xact_old_meta.coh
@ -587,8 +587,8 @@ class L2AcquireTracker(trackerId: Int) extends L2XactTracker {
// State holding transaction metadata // State holding transaction metadata
val xact = Reg(Bundle(new AcquireFromSrc, { case TLId => params(InnerTLId) })) val xact = Reg(Bundle(new AcquireFromSrc, { case TLId => params(InnerTLId) }))
val data_buffer = Reg(init=Vec(UInt(0, width = innerDataBits), innerDataBeats)) val data_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits)))
val wmask_buffer = Reg(init=Vec(UInt(0, width = innerDataBits/8), innerDataBeats)) val wmask_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits/8)))
val xact_tag_match = Reg{ Bool() } val xact_tag_match = Reg{ Bool() }
val xact_way_en = Reg{ Bits(width = nWays) } val xact_way_en = Reg{ Bits(width = nWays) }
val xact_old_meta = Reg{ new L2Metadata } val xact_old_meta = Reg{ new L2Metadata }
@ -980,7 +980,7 @@ class L2WritebackUnit(trackerId: Int) extends L2XactTracker {
val state = Reg(init=s_idle) val state = Reg(init=s_idle)
val xact = Reg(new L2WritebackReq) val xact = Reg(new L2WritebackReq)
val data_buffer = Reg(init=Vec(UInt(0, width = innerDataBits), innerDataBeats)) val data_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits)))
val xact_addr_block = Cat(xact.tag, xact.idx) val xact_addr_block = Cat(xact.tag, xact.idx)
val pending_irels = val pending_irels =