riscv/rocket-chip
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bootrom: follow SBI (a0=hartid, a1=dtb)

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Wesley W. Terpstra committed 2017-03-24 18:18:01 -07:00
1 parent 9a2f0d01a1
commit 34f8ce653a
7 files changed
+36 -28
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src/main/scala/rocketchip/Periphery.scala
+1 -1
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@@ -307,7 +307,7 @@ trait PeripheryBootROM {
private val bootrom_address = 0x1000
private val bootrom_size = 0x1000
private lazy val bootrom_contents = GenerateBootROM(p, bootrom_address, coreplex.dtb)
private lazy val bootrom_contents = GenerateBootROM(coreplex.dtb)
val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, bootrom_contents, true, peripheryBusConfig.beatBytes))
bootrom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
}