riscv/rocket-chip
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Various Chisel3 compatibility changes

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This commit is contained in:
Andrew Waterman 2015-08-03 18:54:56 -07:00
parent 0c9a7817b6
commit 34b9a7fdc5
7 changed files with 12 additions and 12 deletions
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2
Makefrag
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@ -11,7 +11,7 @@ CXXFLAGS := -O1
SBT := java -Xmx2048M -Xss8M -XX:MaxPermSize=128M -jar sbt-launch.jar
SHELL := /bin/bash
CHISEL_ARGS := $(MODEL) --W0W --backend $(BACKEND) --configInstance $(PROJECT).$(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir)
CHISEL_ARGS := $(MODEL) --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configInstance $(PROJECT).$(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir)
src_path = src/main/scala
default_submodules = . junctions uncore hardfloat rocket zscale

2
chisel

@ -1 +1 @@
Subproject commit 8ae531312ff1e1670d690b61297f275474f92bd6
Subproject commit 24ce6c45773d3a0a4e8363943e7f95eaa5600ef7

2
hardfloat

@ -1 +1 @@
Subproject commit 2f5eebd75ff6bdbf10068bbad9fe948bf979d081
Subproject commit d0db2c452f629b334d921280199355c44fc97a3b

2
rocket

@ -1 +1 @@
Subproject commit 0eefb35b2e8d5f8dd975c460f446ad4f232d8ef0
Subproject commit ebb33f2f4b658211960a4c6c023c139420c67212

12
src/main/scala/RocketChip.scala
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@ -103,9 +103,9 @@ class MultiChannelTop extends Module with TopLevelParameters {
// Connect the uncore to the tile memory ports, HostIO and MemIO
uncore.io.tiles_cached <> tileList.map(_.io.cached)
uncore.io.tiles_uncached <> tileList.map(_.io.uncached)
uncore.io.host <> io.host
uncore.io.mem <> io.mem
if(params(UseBackupMemoryPort)) { uncore.io.mem_backup_ctrl <> io.mem_backup_ctrl }
io.host <> uncore.io.host
io.mem <> uncore.io.mem
if(params(UseBackupMemoryPort)) { io.mem_backup_ctrl <> uncore.io.mem_backup_ctrl }
}
/** Wrapper around everything that isn't a Tile.
@ -133,7 +133,7 @@ class Uncore extends Module with TopLevelParameters {
// Wire the htif to the memory port(s) and host interface
io.host.debug_stats_pcr := htif.io.host.debug_stats_pcr
htif.io.cpu <> io.htif
outmemsys.io.mem <> io.mem
io.mem <> outmemsys.io.mem
if(params(UseBackupMemoryPort)) {
outmemsys.io.mem_backup_en := io.mem_backup_ctrl.en
VLSIUtils.padOutHTIFWithDividedClock(htif.io, outmemsys.io.mem_backup, io.mem_backup_ctrl, io.host, htifW)
@ -188,7 +188,7 @@ class OuterMemorySystem extends Module with TopLevelParameters {
val arb = Module(new RocketChipTileLinkArbiter(managerDepths = backendBuffering))(outerTLParams)
val conv = Module(new MemPipeIOTileLinkIOConverter(nMemReqs))(outerTLParams)
arb.io.clients <> banks.map(_.outerTL)
conv.io.tl <> arb.io.managers.head
arb.io.managers.head <> conv.io.tl
MemIOMemPipeIOConverter(conv.io.mem)
} else {
val arb = Module(new RocketChipTileLinkArbiter(managerDepths = backendBuffering))(outerTLParams)
@ -196,7 +196,7 @@ class OuterMemorySystem extends Module with TopLevelParameters {
val conv2 = Module(new MemIONASTISlaveIOConverter(params(CacheBlockOffsetBits)))
val conv3 = Module(new MemPipeIOMemIOConverter(nMemReqs))
arb.io.clients <> banks.map(_.outerTL)
conv1.io.tl <> arb.io.managers.head
arb.io.managers.head <> conv1.io.tl
conv2.io.nasti <> conv1.io.nasti
conv3.io.cpu.req_cmd <> Queue(conv2.io.mem.req_cmd, 2)
conv3.io.cpu.req_data <> Queue(conv2.io.mem.req_data, mifDataBeats)

2
src/main/scala/Vlsi.scala
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@ -24,7 +24,7 @@ object VLSIUtils {
val arb = Module(new MemIOArbiter(nMemChannels))
val mem_serdes = Module(new MemSerdes(htifWidth))
mem_serdes.io.wide <> arb.io.outer
mem_serdes.io.narrow <> backup
backup <> mem_serdes.io.narrow
llcs zip mems zip arb.io.inner foreach { case ((llc, mem), wide) =>
llc.req_cmd.ready := Mux(en, wide.req_cmd.ready, mem.req_cmd.ready)

2
uncore

@ -1 +1 @@
Subproject commit 1ea793c0404dc71600e86fca34ac3d1e60e26a14
Subproject commit 6163ca6793581bc528bb789812b01af24f4dda7c