From 34b9a7fdc54a106f20c084f94121afa862cc295e Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Mon, 3 Aug 2015 18:54:56 -0700
Subject: [PATCH] Various Chisel3 compatibility changes

---
 Makefrag                        |  2 +-
 chisel                          |  2 +-
 hardfloat                       |  2 +-
 rocket                          |  2 +-
 src/main/scala/RocketChip.scala | 12 ++++++------
 src/main/scala/Vlsi.scala       |  2 +-
 uncore                          |  2 +-
 7 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/Makefrag b/Makefrag
index 1fec0ce4..0f9043d3 100644
--- a/Makefrag
+++ b/Makefrag
@@ -11,7 +11,7 @@ CXXFLAGS := -O1
 SBT := java -Xmx2048M -Xss8M -XX:MaxPermSize=128M -jar sbt-launch.jar
 SHELL := /bin/bash
 
-CHISEL_ARGS := $(MODEL) --W0W --backend $(BACKEND) --configInstance $(PROJECT).$(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir)
+CHISEL_ARGS := $(MODEL) --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configInstance $(PROJECT).$(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir)
 
 src_path = src/main/scala
 default_submodules = . junctions uncore hardfloat rocket zscale
diff --git a/chisel b/chisel
index 8ae53131..24ce6c45 160000
--- a/chisel
+++ b/chisel
@@ -1 +1 @@
-Subproject commit 8ae531312ff1e1670d690b61297f275474f92bd6
+Subproject commit 24ce6c45773d3a0a4e8363943e7f95eaa5600ef7
diff --git a/hardfloat b/hardfloat
index 2f5eebd7..d0db2c45 160000
--- a/hardfloat
+++ b/hardfloat
@@ -1 +1 @@
-Subproject commit 2f5eebd75ff6bdbf10068bbad9fe948bf979d081
+Subproject commit d0db2c452f629b334d921280199355c44fc97a3b
diff --git a/rocket b/rocket
index 0eefb35b..ebb33f2f 160000
--- a/rocket
+++ b/rocket
@@ -1 +1 @@
-Subproject commit 0eefb35b2e8d5f8dd975c460f446ad4f232d8ef0
+Subproject commit ebb33f2f4b658211960a4c6c023c139420c67212
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index c261f2c0..ab0d3544 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -103,9 +103,9 @@ class MultiChannelTop extends Module with TopLevelParameters {
   // Connect the uncore to the tile memory ports, HostIO and MemIO
   uncore.io.tiles_cached <> tileList.map(_.io.cached)
   uncore.io.tiles_uncached <> tileList.map(_.io.uncached)
-  uncore.io.host <> io.host
-  uncore.io.mem <> io.mem
-  if(params(UseBackupMemoryPort)) { uncore.io.mem_backup_ctrl <> io.mem_backup_ctrl }
+  io.host <> uncore.io.host
+  io.mem <> uncore.io.mem
+  if(params(UseBackupMemoryPort)) { io.mem_backup_ctrl <> uncore.io.mem_backup_ctrl }
 }
 
 /** Wrapper around everything that isn't a Tile.
@@ -133,7 +133,7 @@ class Uncore extends Module with TopLevelParameters {
   // Wire the htif to the memory port(s) and host interface
   io.host.debug_stats_pcr := htif.io.host.debug_stats_pcr
   htif.io.cpu <> io.htif
-  outmemsys.io.mem <> io.mem
+  io.mem <> outmemsys.io.mem
   if(params(UseBackupMemoryPort)) {
     outmemsys.io.mem_backup_en := io.mem_backup_ctrl.en
     VLSIUtils.padOutHTIFWithDividedClock(htif.io, outmemsys.io.mem_backup, io.mem_backup_ctrl, io.host, htifW)
@@ -188,7 +188,7 @@ class OuterMemorySystem extends Module with TopLevelParameters {
       val arb = Module(new RocketChipTileLinkArbiter(managerDepths = backendBuffering))(outerTLParams)
       val conv = Module(new MemPipeIOTileLinkIOConverter(nMemReqs))(outerTLParams)
       arb.io.clients <> banks.map(_.outerTL)
-      conv.io.tl <> arb.io.managers.head
+      arb.io.managers.head <> conv.io.tl
       MemIOMemPipeIOConverter(conv.io.mem)
     } else {
       val arb = Module(new RocketChipTileLinkArbiter(managerDepths = backendBuffering))(outerTLParams)
@@ -196,7 +196,7 @@ class OuterMemorySystem extends Module with TopLevelParameters {
       val conv2 = Module(new MemIONASTISlaveIOConverter(params(CacheBlockOffsetBits)))
       val conv3 = Module(new MemPipeIOMemIOConverter(nMemReqs))
       arb.io.clients <> banks.map(_.outerTL)
-      conv1.io.tl <> arb.io.managers.head
+      arb.io.managers.head <> conv1.io.tl
       conv2.io.nasti <> conv1.io.nasti
       conv3.io.cpu.req_cmd <> Queue(conv2.io.mem.req_cmd, 2)
       conv3.io.cpu.req_data <> Queue(conv2.io.mem.req_data, mifDataBeats)
diff --git a/src/main/scala/Vlsi.scala b/src/main/scala/Vlsi.scala
index 22007e9d..1e71ec84 100644
--- a/src/main/scala/Vlsi.scala
+++ b/src/main/scala/Vlsi.scala
@@ -24,7 +24,7 @@ object VLSIUtils {
     val arb = Module(new MemIOArbiter(nMemChannels))
     val mem_serdes = Module(new MemSerdes(htifWidth))
     mem_serdes.io.wide <> arb.io.outer
-    mem_serdes.io.narrow <> backup
+    backup <> mem_serdes.io.narrow
 
     llcs zip mems zip arb.io.inner foreach { case ((llc, mem), wide) =>
       llc.req_cmd.ready := Mux(en, wide.req_cmd.ready, mem.req_cmd.ready)
diff --git a/uncore b/uncore
index 1ea793c0..6163ca67 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 1ea793c0404dc71600e86fca34ac3d1e60e26a14
+Subproject commit 6163ca6793581bc528bb789812b01af24f4dda7c