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Various Chisel3 compatibility changes

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This commit is contained in:
Andrew Waterman
2015-08-03 18:54:56 -07:00
parent 0c9a7817b6
commit 34b9a7fdc5
7 changed files with 12 additions and 12 deletions
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2
src/main/scala/Vlsi.scala
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@ -24,7 +24,7 @@ object VLSIUtils {
val arb = Module(new MemIOArbiter(nMemChannels))
val mem_serdes = Module(new MemSerdes(htifWidth))
mem_serdes.io.wide <> arb.io.outer
mem_serdes.io.narrow <> backup
backup <> mem_serdes.io.narrow
llcs zip mems zip arb.io.inner foreach { case ((llc, mem), wide) =>
llc.req_cmd.ready := Mux(en, wide.req_cmd.ready, mem.req_cmd.ready)