riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

syncregs: Make Reset catcher use the synchronizer primitive

Browse Source
This commit is contained in:
Megan Wachs 2017-08-24 17:26:38 -07:00
parent c78ee9f0e4
commit 3461cb47cc
2 changed files with 2 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/main/scala/util/ResetCatchAndSync.scala
View File

@ -15,12 +15,7 @@ class ResetCatchAndSync (sync: Int = 3) extends Module {
val sync_reset = Bool(OUTPUT)
}
val reset_n_catch_reg = Module (new AsyncResetRegVec(sync, 0))
reset_n_catch_reg.io.en := Bool(true)
reset_n_catch_reg.io.d := Cat(Bool(true), reset_n_catch_reg.io.q >> 1)
io.sync_reset := ~reset_n_catch_reg.io.q(0)
io.sync_reset := ~AsyncResetSynchronizerShiftReg(Bool(true), sync)
}

2
src/main/scala/util/SynchronizingReg.scala
View File

@ -31,7 +31,7 @@ abstract class AbstractSynchronizerReg(w: Int = 1, sync: Int = 3) extends Module
object AbstractSynchronizerReg {
def apply [T <: Chisel.Data](gen: (Int, Int) => AbstractSynchronizerReg, in: T, sync: Int = 3, name: Option[String] = None): T = {
val sync_reg = Module(gen(in.getWidth, sync))
val sync_chain = Module(gen(in.getWidth, sync))
name.foreach{ sync_reg.suggestName(_) }
sync_reg.io.d := in.asUInt
(in.chiselCloneType).fromBits(sync_reg.io.q)