diff --git a/src/main/scala/util/ResetCatchAndSync.scala b/src/main/scala/util/ResetCatchAndSync.scala
index f3f68a95..776d94d4 100644
--- a/src/main/scala/util/ResetCatchAndSync.scala
+++ b/src/main/scala/util/ResetCatchAndSync.scala
@@ -15,12 +15,7 @@ class ResetCatchAndSync (sync: Int = 3) extends Module {
     val sync_reset = Bool(OUTPUT)
   }
 
-  val reset_n_catch_reg = Module (new AsyncResetRegVec(sync, 0))
-
-  reset_n_catch_reg.io.en := Bool(true)
-  reset_n_catch_reg.io.d  := Cat(Bool(true), reset_n_catch_reg.io.q >> 1)
-
-  io.sync_reset := ~reset_n_catch_reg.io.q(0)
+  io.sync_reset := ~AsyncResetSynchronizerShiftReg(Bool(true), sync)
 
 }
 
diff --git a/src/main/scala/util/SynchronizingReg.scala b/src/main/scala/util/SynchronizingReg.scala
index a77e9b17..08069c71 100644
--- a/src/main/scala/util/SynchronizingReg.scala
+++ b/src/main/scala/util/SynchronizingReg.scala
@@ -31,7 +31,7 @@ abstract class AbstractSynchronizerReg(w: Int = 1, sync: Int = 3) extends Module
 object AbstractSynchronizerReg {
 
   def apply [T <: Chisel.Data](gen: (Int, Int) => AbstractSynchronizerReg, in: T, sync: Int = 3, name: Option[String] = None): T = {
-    val sync_reg = Module(gen(in.getWidth, sync))
+    val sync_chain = Module(gen(in.getWidth, sync))
     name.foreach{ sync_reg.suggestName(_) }
     sync_reg.io.d := in.asUInt
       (in.chiselCloneType).fromBits(sync_reg.io.q)