riscv/rocket-chip
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coreplex: remove superfluous sink and source from wrapper

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This commit is contained in:
Henry Cook 2017-07-27 14:23:03 -07:00
parent c9e467a668
commit 33852ef965
1 changed files with 0 additions and 2 deletions
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src/main/scala/coreplex/RocketCoreplex.scala
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@ -57,8 +57,6 @@ trait HasRocketTiles extends HasSystemBus
} }
case RationalCrossing(direction) => { case RationalCrossing(direction) => {
val wrapper = LazyModule(new RationalRocketTile(c, i)(pWithExtra)) val wrapper = LazyModule(new RationalRocketTile(c, i)(pWithExtra))
val sink = LazyModule(new TLRationalCrossingSink(direction))
val source = LazyModule(new TLRationalCrossingSource)
sbus.fromRationalTiles(direction) :=* wrapper.masterNode sbus.fromRationalTiles(direction) :=* wrapper.masterNode
wrapper.slaveNode :*= pbus.toRationalSlaves wrapper.slaveNode :*= pbus.toRationalSlaves
wrapper wrapper