riscv/rocket-chip
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Get rid of paddrBits from SystemBus (#1029)

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Andrew Waterman 2017-10-04 12:11:37 -07:00 committed by GitHub
parent 5232a29d7d
commit 32fda51a2c
2 changed files with 6 additions and 3 deletions
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8
src/main/scala/coreplex/RocketCoreplex.scala
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@ -109,8 +109,12 @@ trait HasRocketTilesModuleImp extends LazyModuleImp
with HasPeripheryDebugModuleImp { with HasPeripheryDebugModuleImp {
val outer: HasRocketTiles val outer: HasRocketTiles
// TODO make this less gross and/or support tiles with differently sized reset vectors def resetVectorBits: Int = {
def resetVectorBits: Int = outer.paddrBits // Consider using the minimum over all widths, rather than enforcing homogeneity
val vectors = outer.rocket_tiles.map(_.module.io.reset_vector)
require(vectors.tail.forall(_.getWidth == vectors.head.getWidth))
vectors.head.getWidth
}
val rocket_tile_inputs = dontTouch(Wire(Vec(outer.nRocketTiles, new ClockedRocketTileInputs()(p.alterPartial { val rocket_tile_inputs = dontTouch(Wire(Vec(outer.nRocketTiles, new ClockedRocketTileInputs()(p.alterPartial {
case SharedMemoryTLEdge => outer.sharedMemoryTLEdge case SharedMemoryTLEdge => outer.sharedMemoryTLEdge
})))) // dontTouch keeps constant prop from sucking these signals into the tile })))) // dontTouch keeps constant prop from sucking these signals into the tile

1
src/main/scala/coreplex/SystemBus.scala
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@ -125,5 +125,4 @@ trait HasSystemBus extends HasInterruptBus {
val sbus = LazyModule(new SystemBus(sbusParams)) val sbus = LazyModule(new SystemBus(sbusParams))
def sharedMemoryTLEdge: TLEdge = sbus.busView def sharedMemoryTLEdge: TLEdge = sbus.busView
def paddrBits: Int = sbus.busView.bundle.addressBits
} }