From 32fda51a2c1877f4aa5fdc7834e0212bf0ec49db Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 4 Oct 2017 12:11:37 -0700 Subject: [PATCH] Get rid of paddrBits from SystemBus (#1029) --- src/main/scala/coreplex/RocketCoreplex.scala | 8 ++++++-- src/main/scala/coreplex/SystemBus.scala | 1 - 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/main/scala/coreplex/RocketCoreplex.scala b/src/main/scala/coreplex/RocketCoreplex.scala index e0db5333..211ccaa5 100644 --- a/src/main/scala/coreplex/RocketCoreplex.scala +++ b/src/main/scala/coreplex/RocketCoreplex.scala @@ -109,8 +109,12 @@ trait HasRocketTilesModuleImp extends LazyModuleImp with HasPeripheryDebugModuleImp { val outer: HasRocketTiles - // TODO make this less gross and/or support tiles with differently sized reset vectors - def resetVectorBits: Int = outer.paddrBits + def resetVectorBits: Int = { + // Consider using the minimum over all widths, rather than enforcing homogeneity + val vectors = outer.rocket_tiles.map(_.module.io.reset_vector) + require(vectors.tail.forall(_.getWidth == vectors.head.getWidth)) + vectors.head.getWidth + } val rocket_tile_inputs = dontTouch(Wire(Vec(outer.nRocketTiles, new ClockedRocketTileInputs()(p.alterPartial { case SharedMemoryTLEdge => outer.sharedMemoryTLEdge })))) // dontTouch keeps constant prop from sucking these signals into the tile diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala index 6721ead8..7096b3e5 100644 --- a/src/main/scala/coreplex/SystemBus.scala +++ b/src/main/scala/coreplex/SystemBus.scala @@ -125,5 +125,4 @@ trait HasSystemBus extends HasInterruptBus { val sbus = LazyModule(new SystemBus(sbusParams)) def sharedMemoryTLEdge: TLEdge = sbus.busView - def paddrBits: Int = sbus.busView.bundle.addressBits }